Verify or read pulse for phase change memory and switch
View Patent ↗Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
1. A method, comprising:
applying a read or verify pulse to a phase change memory cell, wherein the read or verify pulse reaches approximately a first voltage level for a first period of time; and
detecting a threshold event for the phase change memory cell during a sense window, wherein the sense window is a time period for which a sensing circuit is configured to detect the threshold event,
wherein the sense window opens after the read or verify pulse reaches the first voltage level, wherein the read or verify pulse is at or below the first voltage level while the sense window is open, and wherein the sense window closes after an expiration of the first period of time.
2. The method of claim 1 , wherein the first voltage level comprises a voltage level sufficient to result in the threshold event if the phase change memory cell is in a substantially crystalline state and insufficient to result in the threshold event if the phase change memory cell is in a substantially amorphous state.
3. The method of claim 2 , further comprising reducing the read or verify pulse to a voltage level lower than the first voltage level and equal to or greater than a second voltage level for a second period of time following the first period of time, wherein the second voltage level comprises a voltage level sufficient to maintain a conductive state of the phase change memory cell.
4. The method of claim 3 , wherein the sense window closes at a second point in time after the expiration of the first period of time and before an expiration of the second period of time or at a point in time after the expiration of the second period of time.
5. The method of claim 4 , wherein the sense window opens at a point in time before the expiration of the first period of time or at a point in time during the second period of time.
6. The method of claim 1 , wherein said detecting the threshold event comprises detecting an increase in current through the phase change memory cell.
7. The method of claim 1 , wherein said detecting the threshold event comprises detecting an increase in voltage across a load resistor configured in series with the phase change memory cell.
8. The method of claim 1 , wherein the sense window is opened after the read or verify pulse has been reduced to a second voltage level that is less than the first voltage level.
9. The method of claim 8 , wherein the second voltage level is greater than a hold voltage, wherein the hold voltage comprises a voltage level sufficient to maintain a conductive state in a PCMS cell.
10. An apparatus, comprising:
a phase change memory cell;
a control circuit for controlling an application of a read or verify pulse to the phase change memory cell, wherein the read or verify pulse reaches a first voltage level for a first period of time; and
a sensing circuit for detecting a threshold event for the phase change memory cell during a sense window, wherein the sense window is a time period for which the sensing circuit is configured to detect the threshold event,
wherein the sensing circuit is configured to open the sense window after the read or verify pulse reaches the first voltage level, wherein the control circuit is configured to maintain the read or verify pulse at or below the first voltage level while the sense window is open, and wherein the sensing circuit is configured to close the sense window after an expiration of the first period of time.
11. The apparatus of claim 10 , wherein the first voltage level comprises a voltage level sufficient to result in the threshold event if the phase change memory cell is in a substantially crystalline state.
12. The apparatus of claim 11 , wherein the control circuit is configured to reduce the read or verify pulse to a voltage level lower than the first voltage level and greater than a second voltage level for a second period of time following the first period of time, wherein the second voltage level comprises a voltage level sufficient to maintain a conductive state of the phase change memory cell.
13. The apparatus of claim 12 , wherein the control circuit is configured to close the sense window at a second point in time after the expiration of the first period of time and before an expiration of the second period of time or at a point in time after the expiration of the second period of time.
14. The apparatus of claim 13 , wherein the control circuit is configured to open the sense window at a point in time before the expiration of the first period of time or at a point in time during the second period of time.
15. The apparatus of claim 10 , wherein the sensing circuit is configured to detect the threshold event at least in part by detecting an increase in current through the phase change memory cell.
16. The apparatus of claim 10 , wherein the sensing circuit is configured to detect the threshold event at least in part by detecting an increase in voltage across a load resistor configured in series with the phase change memory cell.