Memory instruction including parameter to affect operating condition of memory
View Patent ↗Subject matter disclosed herein relates to techniques to operate memory.
1. A method comprising:
receiving a memory instruction comprising:
a command to operate at a location in a memory, and
at least one operating parameter; and
affecting a physical operating condition of peripheral circuitry in said memory based, at least in part, on said at least one operating parameter.
2. The method of claim 1 , wherein said physical operating condition comprises a bias voltage or current level applied to one or more memory cells included in said memory.
3. The method of claim 1 , wherein said physical operating condition comprises at least one of a threshold voltage, a threshold current, and a time duration to distinguish between memory cell logic levels.
4. The method of claim 1 , wherein said physical operating condition comprises at least one of a precision of said memory and an operating speed of said memory.
5. The method of claim 1 , wherein said at least one operating parameter comprises a digital signal.
6. The method of claim 5 , further comprising converting said digital signal to an analog signal.
7. The method of claim 5 , further comprising:
generating a voltage or current corresponding to said digital signal; and
applying said voltage or current to one or more peripheral circuits included in said memory.
8. The method of claim 1 , wherein said command comprises a command to: read from said memory, write to said memory, or to erase at least a portion of said memory.
9. The method of claim 1 , further comprising:
receiving an additional operating parameter included with said instruction, wherein said additional operating parameter is indicative of whether said at least one operating parameter is to be applied during subsequent instructions.
10. A memory device comprising:
circuitry to:
read from or write to an array of memory cells, and receive a memory instruction comprising:
a command to operate at a location in said array of memory cells; and
at least one operating parameter; and
a parameter management block to:
receive the at least one operating parameter, and
affect a physical operating condition of said circuitry based, at least in part, on said at least one operating parameter.
11. The memory device of claim 10 , wherein said physical operating condition comprises a bias voltage or current level applied to one or more memory cells included in said memory.
12. The memory device of claim 10 , wherein said physical operating condition comprises at least one of a threshold voltage, a threshold current, and a time duration to distinguish between memory cell logic levels.
13. The memory device of claim 10 , wherein said physical operating condition comprises at least one of a precision of said memory and an operating speed of said memory.
14. The memory device of claim 10 , further comprising a generator to generate voltage or current levels based, at least in part, on said at least one operating parameter.
15. The memory device of claim 10 , further comprising:
a first input port to receive said at least one operating parameter; and
a second input port to receive said command.
16. The memory device of claim 10 , said circuitry further to receive an address descriptive of said location in said array of memory cells.
17. A system comprising:
a memory device comprising an array of memory cells, said memory device further comprising a memory controller to:
write to or read from said array of memory cells;
receive a memory instruction comprising:
a command to operate at a location in said array of memory cells; and
at least one operating parameter; and
affect a physical operating condition of peripheral circuitry in said memory device based, at least in part, on said at least one operating parameter; and
a processor to host one or more applications and to initiate said memory instruction to said memory controller to provide access to said array of memory cells.
18. The system of claim 17 , wherein said physical operating condition comprises a bias voltage or current level applied to one or more memory cells included in said memory.
19. The system of claim 17 , wherein said physical operating condition comprises at least one of a threshold voltage, a threshold current, and a time duration to distinguish between memory cell logic levels.
20. The system of claim 17 , wherein said physical operating condition comprises at least one of a precision and an operating speed of said memory.
21. The method of claim 1 , wherein said affecting the physical operating condition of the peripheral circuitry occurs during execution of the memory instruction.
22. The memory device of claim 10 , wherein the physical operating condition is affected during execution of the memory instruction.
23. The system of claim 17 , wherein the physical operating condition is affected during execution of the memory instruction.