Transactional memory
View Patent ↗Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
1. A method comprising:
receiving a transaction command comprising a transaction request, or multiple transaction operators;
copying original contents in a first portion of a memory array to a second portion of said memory array in response to receiving said transaction request, wherein said memory array is a phase change memory (PCM) array and wherein said memory array is on one memory die; and
modifying said original contents of said second portion in response to receiving said multiple transaction operators of said transaction command;
providing a master remap table pointing to physical locations in said memory array;
providing a temporary remap table corresponding to a portion of said master remap table affected by said transaction command;
modifying said temporary remap table to reflect modifications made to said second portion of said memory array; and
updating said master remap table based on modified contents of said temporary remap table.
2. The method of claim 1 , wherein said transaction command further comprises a transaction commit to conclude said transaction command, and in response to receiving said transaction commit, determining whether a transaction associated with said transaction command was successful or failed; and
if said transaction was successful:
replacing said original contents of said first portion with said modified contents in said second portion, and if said transaction failed:
rewriting over said modified contents in said second portion during a subsequent transaction.
3. The method of claim 1 , wherein said temporary remap table points to a physical location in said memory where said second portion is located.
4. The method of claim 3 , further comprising:
modifying said temporary remap table in response to receiving said one or more transaction operators.
5. The method of claim 3 , further comprising:
simultaneously maintaining one or more additional temporary remap tables corresponding to one or more additional transactions.
6. The method of claim 1 , further comprising:
determining a maximum number of allowed transaction operators and/or a maximum size of said portion of said memory based, at least in part, on contents of a register.
7. The method of claim 3 , further comprising:
modifying said master remap table in response to receiving a transaction commit in said transaction command and in response to memory wear-leveling operations or bad memory-replacement operations.
8. A memory device comprising:
at least one memory array; and
a controller to:
receive a transaction command comprising a transaction request or multiple transaction operators;
copy original contents in a first portion of said at least one memory array to a second portion of said at least one memory array in response to receiving said transaction request, wherein said at least one memory array is a phase change memory (PCM) array and wherein said at least one memory array is on one memory die;
modify said original contents of said second portion in response to receiving said multiple transaction operators of said transaction command;
provide a master remap table pointing to physical locations in said at least one memory array;
provide a temporary remap table corresponding to a portion of said master remap table affected by said transaction command;
modify said temporary remap table to reflect modifications made to said second portion of said at least one memory array; and
update said master remap table based on modified contents of said temporary remap table.
9. The memory device of claim 8 , wherein said temporary remap table points to a physical location in said at least one memory array where said second portion is located.
10. The memory device of claim 9 , wherein said controller is adapted to:
modify said temporary remap table in response to receiving said one or more transaction operators.
11. The memory device of claim 9 , further comprising:
one or more additional temporary remap tables corresponding to one or more additional transactions.
12. The memory device of claim 8 , further comprising:
a register to store contents to indicate a maximum number of allowed transaction operators and/or a maximum size of said portion of said at least one memory array.
13. The memory device of claim 9 , wherein said master remap table points to physical locations in said at least one memory array based, at least in part, on said one or more transaction operators and based, at least in part, on memory wear-leveling operations or bad memory-replacement operations.
14. The memory device of claim 8 , further comprising:
a spare area of said memory array to maintain said second portion.
15. The memory device of claim 8 , wherein said controller comprises a transaction engine that operates based, at least in part, on a transaction protocol.
16. A system comprising:
a memory device comprising at least one memory array, wherein said at least one memory array is a phase change memory (PCM) array and wherein said at least one memory array is on one memory die, said memory device further comprising a memory controller to:
receive a transaction command comprising a transaction request, or multiple transaction operators;
copy original contents in a first portion of said at least one memory array to a second portion of said at least one memory array in response to receiving said transaction request; and
modify said original contents of said second portion in response to receiving said multiple transaction operators of said transaction command;
provide a master remap table pointing to physical locations in said at least one memory array;
provide a temporary remap table corresponding to a portion of said master remap table affected by said transaction command;
modify said temporary remap table to reflect modifications made to said second portion of said at least one memory array;
update said master remap table based on modified contents of said temporary remap table; and
a processor to host one or more applications and to initiate said transaction command.
17. The system of claim 16 , wherein said temporary remap table points to a physical location in said at least one memory array where said second portion is located.
18. The system of claim 17 , wherein said memory controller is adapted to:
modify said temporary remap table in response to receiving said one or more transaction operators.
19. The system of claim 17 , further comprising:
one or more additional temporary remap tables corresponding to one or more additional transactions.
20. The system of claim 16 , wherein said controller comprises a transaction engine that operates based, at least in part, on a transaction protocol.