Granted Patent B1

US 8,014,208 · App. 12/357,940 · Granted Sep 6, 2011

Abstract

Claims (43)

1. A method, comprising:

verifying an erase operation for a flash memory device using, at least in part, a program operation verification circuit within the flash memory device, the flash memory device to perform a command for erasing one or more blocks located in one or more planes and a separate command for erase verifying one or more blocks located in one or more planes, wherein said verifying the erase operation further comprises latching a first signal at a first latch of a first page buffer of a plurality of page buffers, the first signal to indicate whether the page buffer comprises a redunded page buffer.

2. The method of claim 1 , wherein said verifying the erase operation comprises receiving a plurality of signals from the plurality of page buffers at a combinatorial logic circuit, and generating an output signal indicating a pass/fail condition using the combinatorial logic circuit based, at least in part, on the plurality of signals from the plurality of page buffers.

3. The method of claim 2 , wherein said plurality of signals from the plurality of page buffers comprise a plurality of erase verification signals indicating, at least in part, whether a plurality of memory cells associated with the plurality of page buffers have been successfully erased.

4. The method of claim 1 , wherein said verifying the erase operation further comprises:

determining whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased and storing a second signal indicative of the results of the determination in a second latch of the first page buffer;

transferring the second signal from the second latch to the first latch, the second signal to overwrite the first signal stored at the first latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines associated with the first page buffer are erased; and

generating an erase verification signal associated with the first page buffer at least in part in response to the second signal overwriting the first signal at the first latch.

5. The method of claim 1 , wherein said verifying the erase operation further comprises:

determining whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased and storing a second signal indicative of the results of the determination in a second latch of the first page buffer;

transferring the second signal from the second latch to a first bit line of the one or more bit lines;

resetting the second latch;

transferring the first signal stored at the first latch to the second latch;

resetting the first latch;

transferring the second signal from the first bit line to the first latch;

transferring the second signal from the first latch to the second latch, the second signal from the first latch to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased; and

generating an erase verification signal associated with the first page buffer at least in part in response to the second latch storing the second signal indicating that the plurality of memory cells are erased.

6. The method of claim 1 , wherein said verifying the erase operation further comprises:

determining whether one or more memory cells associated with one or more bit lines associated with the first page buffer are erased and storing a second signal indicative of the results of the determination in a second latch of the first page buffer;

transferring the first signal stored at the first latch to a third latch;

resetting the first latch;

transferring the second signal stored at the second latch to the first latch;

resetting the second latch;

transferring the first signal stored in the third latch to the second latch;

transferring the second signal stored at the first latch to the second latch, the second signal to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased; and

generating an erase verification signal associated with the first page buffer at least in part in response to the second latch storing the second signal indicating that the plurality of memory cells are erased.

7. A flash memory device, comprising:

a program operation verification circuit to verify, at least in part, an erase operation; and

a first page buffer of a plurality of page buffers, the first page buffer including a first latch to latch a first signal indicative of whether the first page buffer comprises a redunded page buffer, the flash memory device further to perform a command for erasing one or more blocks of memory cells located in one or more planes and a separate command for erase verifying one or more blocks of memory cells located in one or more planes.

8. The memory device of claim 7 , the plurality of page buffers to generate a plurality of erase verification signals, wherein the program operation verification circuit comprises a combinatorial logic circuit to receive the plurality of erase verification signals, the combinatorial circuit further to generate an output signal indicating a pass/fail condition based, at least in part, on the plurality of erase verification signals.

9. The memory device of claim 8 , the plurality of erase verification signals to indicate, at least in part, whether a plurality of memory cells associated with the plurality of page buffers have been successfully erased.

10. The memory device of claim 7 , wherein the first page buffer further comprises a second latch coupled to the first latch, the second latch to store a second signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erase, the second signal stored at the second latch to be transferred to the first latch, the second signal to overwrite the first signal stored at the first latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the first latch storing the second signal from the second latch indicating that the plurality of memory cells are erased.

11. The memory device of claim 7 , wherein the first page buffer further comprises a second latch coupled to the first latch, the second latch to store a signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased the results of the determination, the second signal stored at the second latch to be transferred to a first bit line of the one or more bit lines, the second latch to be reset, the first signal stored at the first latch to be transferred to the second latch, the first latch to be reset, the second signal stored at the first bit line to be transferred to the first latch, the second signal stored at the first latch to be transferred to the second latch, the second signal from the first latch to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the second latch storing the second signal from the first latch indicating that the plurality of memory cells are erased.

12. The memory device of claim 7 , wherein the first page buffer further comprises a second latch and a third latch coupled to the first latch, the second latch to store a second signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased, the first signal stored at the first latch to be transferred to the third latch, the first latch to be reset, the second signal stored at the second latch to be transferred to the first latch, the second latch to be reset, the first signal stored at third latch to be transferred to the second latch, the second signal stored at the first latch to be transferred to the second latch, the second signal to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the second latch storing the second signal indicating that the plurality of memory cells are erased.

13. A system, comprising:

a processor; and

a flash memory device coupled to the processor, the memory device comprising a program operation verification circuit adapted to verify, at least in part, an erase operation; and

a first page buffer of a plurality of page buffers, the first page buffer including a first latch to latch a first signal indicative of whether the first page buffer comprises a redunded page buffer, the flash memory device further adapted to perform a command for erasing one or more blocks located in one or more planes and a separate command for erase verifying one or more blocks located in one or more planes.

14. The system of claim 13 , the plurality of page buffers to generate a plurality of erase verification signals, wherein the program operation verification circuit comprises a combinatorial logic circuit to receive the plurality of erase verification signals, the combinatorial circuit further to generate an output signal indicating a pass/fail condition based, at least in part, on the plurality of erase verification signals.

15. The system of claim 14 , the plurality of erase verification signals to indicate, at least in part, whether a plurality of memory cells associated with the plurality of page buffers have been successfully erased.

16. The system of claim 13 , wherein the first page buffer further comprises a second latch coupled to the first latch, the second latch to store a second signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased, the second signal stored at the second latch to be transferred to the first latch, the second signal to overwrite the first signal stored at the first latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the first latch storing the second signal indicating that the memory cells are erased.

17. The system of claim 13 , wherein the first page buffer further comprises a second latch coupled to the first latch, the second latch to store a second signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased, the second signal stored at the second latch to be transferred to a first bit line of the one or more bit lines, the second latch to be reset, the first signal stored at the first latch to be transferred to the second latch, the first latch to be reset, the second signal stored at the first bit line to be transferred to the first latch, the second signal stored at the first latch to be transferred to the second latch, the second signal to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the second latch storing the second signal indicating that the memory cells are erased.

18. The system of claim 13 , wherein the first page buffer further comprises a second latch and a third latch coupled to the first latch, the second latch to store a second signal indicative of whether a plurality of memory cells associated with one or more bit lines associated with the first page buffer are erased, the first signal stored at the first latch to be transferred to the third latch, the first latch to be reset, the second signal stored at the second latch to be transferred to the first latch, the second latch to be reset, the first signal stored at third latch to be transferred to the second latch, the second signal stored at the first latch to be transferred to the second latch, the second signal to overwrite the first signal stored at the second latch at least in part in response to the second signal indicating that the plurality of memory cells associated with the one or more bit lines are erased, the first page buffer to generate an erase verification signal at least in part in response to the second latch storing the second signal indicating that the plurality of memory cells are erased.

Assignments (9)