Write operation for phase change memory

1. A method, comprising:

controlling a plurality of capacitive elements to apply currents having a plurality of level thresholds to a phase change memory cell; and

coupling the plurality of capacitive elements to the phase change memory cell to produce a current pulse of a specified programmable shape in the phase change memory cell.

2. The method of claim 1 , wherein the controlling a plurality of capacitive elements comprises drawing a current pulse exceeding a melt threshold of the phase change memory cell from one or more of the plurality of capacitive elements.

3. The method of claim 2 , wherein the melt threshold comprises a value of approximately 1.2 mA.

4. The method of claim 1 , wherein one or more of the plurality of capacitive elements comprises a parasitic capacitance.

5. The method of claim 1 , wherein one or more of the plurality of capacitive elements comprises an explicitly designed capacitor.

6. The method of claim 1 , wherein the coupling of the plurality of capacitive elements comprises substantially discharging one or more of the plurality of capacitive elements over a relatively brief period to produce a substantially amorphous state.

7. The method of claim 6 , wherein the discharging occurs over a period of no more than approximately 2 ns.

8. The method of claim 1 , wherein the coupling the one or more of the plurality of capacitive elements comprises substantially eliminating the current applied to the phase change memory cell over a relatively brief period to produce a substantially amorphous state at least in part by decoupling the one or more of the plurality of capacitive elements from the phase change memory cell.

9. The method of claim 1 , wherein the coupling the one or more of the plurality of capacitive elements comprises discharging the one or more of the plurality of capacitive elements over a relatively extended period to produce a substantially crystalline state.

10. The method of claim 9 , wherein the coupling the one or more of the plurality of capacitive elements comprises limiting a discharge current through the phase change memory cell to a level less than a melt threshold.

11. The method of claim 10 , wherein the limiting the discharge current through the phase change memory cell comprises engaging a current limiter circuit coupled to a word-line decoder path.

12. The method of claim 9 , wherein the discharging occurs over a period of no more than approximately 200 ns.

13. An apparatus, comprising:

a plurality of capacitive elements to apply currents having a plurality of level thresholds to a phase change memory cell; and

control circuitry to control coupling the plurality of capacitive elements to the phase change memory cell to produce a current pulse of a specified programmable shape in the phase change memory cell.

14. The apparatus of claim 13 , wherein the current pulse of a specified programmable shape comprises a current pulse to exceed a melt threshold of a phase change memory cell.

15. The apparatus of claim 14 , wherein applied currents are to be applied over a period of no more than approximately 6 ns.

16. The apparatus of claim 13 , wherein one or more of the plurality of capacitive elements comprises a parasitic capacitance.

17. The apparatus of claim 13 , wherein one or more of the plurality of capacitive elements comprises an explicitly designed capacitor.

18. The apparatus of claim 13 , wherein the control circuitry is capable of controlling the one or more of the plurality of capacitive elements at least in part by substantially discharging the one or more of the plurality of capacitive elements over a relatively brief period to produce a substantially amorphous state.

19. The apparatus of claim 13 , wherein the control circuitry is capable of controlling a discharge of the one or more of the plurality of capacitive elements at least in part by discharging the one or more of the plurality of capacitive elements over a relatively extended period to produce a substantially crystalline state.

20. The apparatus of claim 19 , wherein the control circuitry comprises a current limiter capable of limiting a discharge current through the phase change memory cell to a level less than the melt threshold.

21. A system, comprising:

a processor; and

a non-volatile memory device coupled to the processor, the non-volatile memory device comprising

a plurality of capacitive elements to apply currents having plurality of level thresholds to a phase change memory cell; and

control circuitry to control coupling the plurality of capacitive elements to the phase change memory cell to produce a current pulse of a specified programmable shape in the phase change memory cell.

22. The system of claim 21 , wherein the current pulse of a specific programmable shape comprises a current pulse to exceed a melt threshold of the phase change memory cell.

23. The system of claim 21 , wherein the control circuitry is capable of controlling the plurality of capacitive elements at least in part by substantially discharging the plurality of capacitive elements over a relatively brief quenching period to produce a substantially amorphous state.

24. The system of claim 21 , wherein the control circuitry is capable of controlling the plurality of capacitive elements at least in part by discharging the capacitive elements over a relatively extended period to produce a substantially crystalline state.

25. The apparatus of claim 24 , wherein the discharging to occur over a period of no more than approximately 200 ns.