Interruption of write memory operations to provide faster read access in a serial interface memory
View Patent ↗After serially receiving several MSBs of the address, a microcontroller may determine whether a write operation is occurring in the same particular partition. If it is determined that a write operation is not occurring in the same partition, then the microcontroller may immediately perform the read operation. If a write operation is occurring, however, then the microcontroller may first begin to interrupt the write operation before beginning the read operation.
1. An electronically-implemented method of accessing memory, the method comprising:
receiving a read command including a first portion of a memory address of a memory device, wherein the first portion of the memory address comprises most significant bits of the memory address and identifies maps to a memory partition of the memory device, wherein the memory address is received serially in an order from most significant bit to least significant bit; and
before receiving all of the memory address, determining if a write operation is being performed in the same memory partition, and if so, then:
automatically interrupting the write operation and while the write operation is interrupted:
serially receiving a second portion of said memory address wherein the second portion is different from the first portion; and
automatically reading contents of said memory partition at said memory address.
2. The method of claim 1 , further comprising:
initiating internal sensing operations to read said contents of said memory partition prior to receiving a final portion of said memory address.
3. The method of claim 1 , wherein said interrupting said write operation is initiated by an internal microcontroller in said memory device.
4. The method of claim 1 , wherein said memory device comprises a phase change memory (PCM).
5. The method of claim 1 , wherein said write operation was initiated by an internal operation of said memory device.
6. The method of claim 1 , further comprising:
resuming said write operation subsequent to completion of said reading said contents of said memory partition.
7. The method of claim 6 , wherein said resuming said write operation is initiated by an internal microcontroller in said memory device.
8. The method of claim 1 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.
9. A microcontroller of a memory device comprising:
at least one interface to connect to a memory array; and
electronic circuitry configured to:
receive a read command including a first portion of a memory address of said memory array, wherein the first portion of the memory address comprises most significant bits of the memory address and identifies a memory partition of the memory device, wherein the memory address is received serially in an order from most significant bit to least significant bit; and
before receiving all of the memory address, determine if a write operation is being performed in the same memory partition, and if so, then:
automatically interrupt the write operation and while the write operation is interrupted:
serially receive a second portion of said memory address, wherein the second portion is different from the first portion; and
automatically read contents of said memory partition at said memory address.
10. The microcontroller of said memory device of claim 9 , further comprising an electronic circuit configured to initiate internal sensing operations to read said contents of said memory partition prior to receiving a final portion of said memory address.
11. The microcontroller of said memory device of claim 9 , wherein said interrupting said write operation is initiated by said microcontroller in said memory device.
12. The microcontroller of said memory device of claim 9 , further comprising a circuit configured to:
resume said write operation subsequent to completion of said reading said contents of said memory partition, wherein said resuming said write operation is initiated by said microcontroller in said memory device.
13. The microcontroller of said memory device of claim 9 , wherein said memory device comprises a serial phase change memory (PCM).
14. The microcontroller of the memory device of claim 9 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.
15. A system comprising:
a memory device comprising a memory array, said memory device further comprising a microcontroller configured to:
receive a read command including a first portion of a memory address of said memory array, wherein the first portion of the memory address comprises most significant bits (MSBs) of the memory address and identifies a memory partition of the memory device, wherein the memory address is received serially in an order from MSB to least significant bit; and
before receiving all of the memory address, determine if a write operation is being performed in the same memory partition, and if so, then:
automatically interrupt the write operation and while the write operation is interrupted:
serially receive a second portion of said memory address, wherein the second portion is different from the first portion; and
automatically read contents of said memory partition at said memory address; and
a processor configured to host one or more applications and configured to initiate said read command to said microcontroller to provide access to said memory array.
16. The system of claim 15 , wherein said microcontroller is adapted to initiate internal sensing operations to read said contents of said memory partition prior to receiving a final portion of said memory address.
17. The system of claim 15 , wherein said interrupting said write operation is initiated by said microcontroller.
18. The system of claim 15 , wherein said microcontroller is adapted to resume said write operation subsequent to completion of said reading said contents of said memory partition, wherein said resuming said write operation is initiated by said microcontroller.
19. The system of claim 15 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.