Erase completion recognition
View Patent ↗Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed.
1. An apparatus of comprising:
a main memory array;
at least one erase status memory cell associated with the main memory array; and
a control module operatively coupled to the at least one erase status memory cell, the control module configured to indicate an erase completion status of the main memory array based at least in part on a value stored in the at least one erase status memory cell;
wherein the control module includes a register configured to connect to an output of the at least one erase status memory cell, the register configured to indicate the erase completion status of the main memory array; and
wherein the control module includes a compare block configured to read the at least one erase status memory cell and update the register on powering up of the apparatus.
2. The apparatus of claim 1 , wherein the main memory array includes a plurality of memory cells arranged in an erase status column, and wherein the erase status column includes the at least one erase status memory cell.
3. The apparatus of claim 1 , wherein the main memory array comprises a plurality of rows of memory cells, and wherein the at least one erase status memory cell is configured to indicate an erase completion status of at least one row of the plurality of TOWS.
4. The apparatus of claim 1 , wherein the register is a bit mask register.
5. The apparatus of claim 1 , wherein the compare block comprises a state machine.
6. The apparatus of claim 1 , wherein the main memory array comprises NOR flash memory cells.
7. An apparatus comprising:
a main memory array;
at least one erase status memory cell associated with the main memory array; and
a control module operatively coupled to the at least one erase status memory cell, the control module configured to indicate an erase completion status of the main memory array based at least in part on a value stored in the at least one erase status memory cell;
wherein the at least one erase status memory cell includes a multi-level memory cell defining multiple programming states; and
wherein the control module is configured to cause a read of the main memory array and the value stored in the at least on erase status memory cell when the multi-level memory cell is in a first programming state, and to cause a read of the main memory array without reading the value stored in the at least on erase status memory cell when the multi-level memory cell is in a second programming state.
8. A method comprising:
erasing one or more memory cells of a main memory array;
after erasing the one or more memory cells, programming at least one erase status memory cell associated with the main memory array to indicate an erase completion status of the main memory array;
programming a register based at least in part on a value stored in the erase completion status memory cell; and
reading the at least one erase status memory cell and updating the register on powering up of the apparatus.
9. The method of claim 8 , wherein the programming of the at least one erase status memory cell comprises programming at least one erase status memory cell to indicate an erase completion status of at least one row of the main memory array.
10. A system comprising:
a memory module including a main memory array and at least one erase status memory cell associated with the main memory array;
a control module operatively coupled to the memory module, the control module configured to indicate an erase completion status of the main memory array based at least in part on a value stored in the at least one erase status memory cell, wherein the control module includes a register configured to connect to an output of the at least one erase status memory cell, the register configured to indicate the erase completion status of the memory module, and wherein the control module includes a compare block configured to read the at least one erase status memory cell and update the register on powering up of the apparatus;
a host logic device bus; and
a bus interface unit operatively coupling the control module and the host logic device bus.
11. The system of claim 10 , wherein the memory module and the control module are embedded in a host logic device.
12. The system of claim 11 , wherein the host logic device is a microcontroller or a digital signal processor.
13. The system of claim 11 , further comprising a processor core operatively coupled to the host logic device bus.
14. The system of claim 10 , wherein the main memory array comprises a plurality of rows of memory cells, and wherein the at least one erase status memory cell is configured to indicate an erase completion status of at least one row of the plurality of TOWS.
15. The system of claim 10 , wherein the system is a selected one of a desktop computer, a laptop computer, a server, a set-top box, a digital recorder, a game console, a personal digital assistant, a mobile phone, a digital media player, or a digital camera.