IP Library Granted Patent US 8,225,042
Granted Patent B1
US 8,225,042 · App. 12/435,986 · Granted Jul 17, 2012

Method and apparatus for preventing foreground erase operations in electrically writable memory devices

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Quick Facts
Patent No.
US 8,225,042
App. No.
12/435,986
Granted
Jul 17, 2012
Kind
B1
Abstract

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory has a memory cache to store data corresponding to a received sector write operation, and a main memory comprising at least the designated memory block and a second memory block. A controller may reclaim at least one sector of the designated memory block and performing a write operation to write information from the memory cache in response to the received sector write operation to at least one sector of the second memory block.

Claims (32)

1. A method, comprising:

performing at least one write operation to a nonvolatile memory cache disposed within a nonvolatile memory device comprising a nonvolatile main memory and the nonvolatile memory cache in response to a received sector write command, the received sector write command corresponding to at least one sector of a designated memory block;

reclaiming the at least one sector of the designated memory block;

performing a write operation to write information from the nonvolatile memory cache based at least in part on the received sector write command to at least one sector of a second memory block.

2. The method of claim 1 , wherein the designated memory block comprises the at least one sector and at least one remainder sector, wherein the reclaiming comprises copying remainder information of the at least one remainder sector to at least one corresponding sector of the second memory block.

3. The method of claim 2 , wherein the reclaiming further comprises erasing information of the designated memory block after copying the information of the at least one remainder sector to at least one corresponding sector of the second memory block.

4. The method of claim 1 , wherein the nonvolatile memory cache comprises at least one cache memory block.

5. The method of claim 1 , wherein the at least one cache memory block has a different size from the designated memory block.

6. The method of claim 2 , further comprising updating a File System Allocation Table to indicate that the remainder information has been moved from the designated memory block to the second memory block.

7. A nonvolatile memory device, comprising:

a nonvolatile memory cache to store data corresponding to a received sector write command corresponding to at least one sector of a designated memory block;

a nonvolatile main memory comprising at least the designated memory block and a second memory block; and

a controller to reclaim the at least one sector of the designated memory block and perform a write operation to write information from the nonvolatile memory cache at least partially in response to the received sector write command to at least one sector of the second memory block.

8. The nonvolatile memory device of claim 7 , wherein the designated memory block comprises the at least one sector and at least one remainder sector, wherein the reclaiming comprises copying remainder information of the at least one remainder sector to at least one corresponding sector of the second memory block.

9. The nonvolatile memory device of claim 8 , wherein the controller is adapted to erase information of the designated memory block after copying the information of the at least one remainder sector to at least one corresponding sector of the second memory block.

10. The nonvolatile memory device of claim 7 , wherein the nonvolatile memory cache comprises at least one cache memory block.

11. The nonvolatile memory device of claim 7 , wherein the at least one cache memory block has a different size from the designated memory block.

12. The nonvolatile memory device of claim 7 , wherein the nonvolatile memory device comprises a flash memory device.

13. The nonvolatile memory device of claim 7 , wherein the nonvolatile memory device comprises a PCM memory.

14. A system, comprising:

a processor to generate and transmit a sector write command;

a nonvolatile memory device to:

receive the sector write command;

perform at least one write operation to a nonvolatile memory cache disposed within of a nonvolatile memory device comprising a nonvolatile main memory and the nonvolatile memory cache based on the received sector write command, the received sector write command corresponding to at least one sector of a designated memory block;

reclaim the at least one sector of the designated memory block; and

perform a write operation to write information from the nonvolatile memory cache at least partially in response to the received sector write command to at least one sector of a second memory block.

15. The system of claim 14 , wherein the designated memory block comprises the at least one sector and at least one remainder sector, wherein the reclaiming comprises copying remainder information of the at least one remainder sector to at least one corresponding sector of the second memory block.

16. The system of claim 15 , wherein the controller is adapted to erase information of the designated memory block after copying the information of the at least one remainder sector to at least one corresponding sector of the second memory block.

17. The system of claim 14 , wherein the nonvolatile memory cache comprises at least one cache memory block.

18. The system of claim 14 , wherein the at least one cache memory block has a different size from the designated memory block.

19. The system of claim 14 , wherein the nonvolatile memory device comprises a flash memory device.

20. The system of claim 14 , wherein the nonvolatile memory device comprises a PCM memory device.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2010
From: RUDELIC, JOHN; DOVER, LANCE
To: NUMONYX B.V.
Reel/Frame 024760/0145 →