IP Library Granted Patent US 8,976,621
Granted Patent B2
US 8,976,621 · App. 13/202,326 · Granted Mar 10, 2015

Continuous page read for memory

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Quick Facts
Patent No.
US 8,976,621
App. No.
13/202,326
Granted
Mar 10, 2015
Kind
B2
Abstract

Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.

Claims (55)

1. A method comprising:

reading a first page of data and providing said first page of data to be stored in a page buffer in response to receiving a first portion of a memory address of said first page;

fetching words of said first page of data stored in said page buffer in response to receiving an additional portion of said memory address of said first page;

monitoring a count of said words fetched from said page buffer; and

in response to said count reaching a particular threshold number less than a number of said words of said first page of data, sensing a second page of data before completing, and while continuing, said fetching words of said first page.

2. The method of claim 1 , further comprising:

providing said second page of data to said page buffer in response to a last word of said first page of data being fetched.

3. The method of claim 1 , wherein initiating said sensing of said second page of data is performed automatically without receiving an address for said second page of data.

4. The method of claim 1 , wherein said first portion of said memory address comprises an address of said first page of data and said additional portion of said memory address comprises least significant bits of said memory address to identify said words of said first page of data.

5. A method comprising:

reading a first page of data and providing said first page of data to be stored in a page buffer in response to receiving a first portion of a memory address of said first page;

fetching words of said first page of data stored in said page buffer in response to receiving an additional portion of said memory address of said first page;

sensing a second page of data before completing said fetching words of said first page; and

toggling said additional portion of said memory address between two values, wherein said fetching said words of said first page of data is performed synchronously with said toggling, and wherein said additional portion of said memory address comprises a single bit of said memory address.

6. The method of claim 1 , wherein said fetching words of said first page is performed synchronously with changing a value of said additional portion of said memory address.

7. The method of claim 1 , wherein said first portion of said memory address corresponds to two or more pages.

8. A memory device comprising:

a controller to:

read a page of data and provide said page of data to be stored in a page buffer in response to receiving a first portion of a memory address of the page of data;

fetch words of said page of data stored in said page buffer in response to receiving an additional portion of said memory address;

monitor a count of said words fetched from said page buffer; and

in response to said count reaching a particular threshold number less than a number of said words of said page of data, read a subsequent page of data before completing, and while continuing, said fetching words of said page of data.

9. The memory device of claim 8 , wherein said controller is adapted to flush said subsequent page of data into said page buffer in response to a last word of said page of data being fetched.

10. The memory device of claim 8 , wherein said controller is configured to initiate said sense of said subsequent page of data automatically without receiving an address for said subsequent page of data.

11. The memory device of claim 8 , wherein said first portion of said memory address comprises an address of said page of data and said additional portion of said memory address comprises least significant bits of said memory address to identify said words of said page of data.

12. A memory device comprising:

a controller to:

read a page of data and provide said page of data to be stored in a page buffer in response to receiving a first portion of a memory address of the page of data;

fetch words of said page of data stored in said page buffer in response to receiving an additional portion of said memory address;

sense a subsequent page of data before completing said fetching words of said page of data; and

toggle said additional portion of said memory address between two values, wherein said fetching said words of said page of data is performed synchronously with said toggling, and wherein said additional portion of said memory address comprises a single bit of said memory address.

13. The memory device of claim 8 , wherein said fetching words of said page is performed synchronously with changing a value of said additional portion of said memory address.

14. The memory device of claim 8 , wherein said first portion of said memory address corresponds to two or more pages.

15. A system comprising:

a memory device comprising an array of memory cells, said memory device further comprising a controller to:

read a page of data and flush said page of data to be stored in a page buffer in response to receiving a first portion of a memory address of said page of data;

fetch words of said page of data stored in said page buffer in response to receiving an additional portion of said memory address;

monitor a count of said words fetched from said page buffer; and

in response to said count reaching a particular threshold number less than a number of said words of said page of data, read a subsequent page of data before completing, and while continuing., said fetching words of said first page; and

a processor to host one or more applications and to initiate a write command to said controller to provide access to said memory cells.

16. The system of claim 15 , wherein said controller is configured to initiate said sense of said subsequent page of data automatically without receiving an address for said subsequent page of data.

17. The system of claim 15 , wherein said first portion of said memory address comprises an address of said page of data and said additional portion of said memory address comprises least significant bits of said memory address to identify said words of said page of data.

18. The method of claim 5 , wherein initiating said sensing of said second page of data is performed automatically without receiving an address for said second page of data.

19. The method of claim 5 , further comprising providing said second page of data to said page buffer in response to a last word of said first page of data being fetched.

20. The memory device of claim 12 , wherein said controller is configured to initiate said sense of said subsequent page of data automatically without receiving an address for said subsequent page of data.

21. The memory device of claim 12 , wherein said controller is configured to flush said subsequent page of data into said page buffer in response to a last word of said page of data being fetched.

22. A system comprising:

a memory device comprising an array of memory cells, said memory device further comprising a controller to:

read a page of data and flush said page of data to be stored in a page buffer in response to receiving a first portion of a memory address of said page of data;

fetch words of said page of data stored in said page buffer in response to receiving an additional portion of said memory address;

sense a subsequent page of data before completing said fetching words of said first page; and

toggle said additional portion of said memory address between two values, wherein said fetching said words of said page of data is performed synchronously with said toggling, and wherein said additional portion of said memory address comprises a single bit of said memory address; and

a processor to host one or more applications and to initiate a write command to said controller to provide access to said memory cells.

23. The system of claim 22 , wherein said controller is configured to initiate said sense of said subsequent page of data automatically without receiving an address for said subsequent page of data.

24. The system of claim 22 , wherein said controller is configured to flush said subsequent page of data into said page buffer in response to a last word of said page of data being fetched.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2011
From: ZHANG, YIHUA; SHEN, JUN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026774/0797 →