Configurable latching for asynchronous memories
View Patent ↗A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.
1. A method comprising:
providing an asynchronous memory with the ability to selectively enter a first synchronous burst read mode or a second synchronous burst read mode based on a signal from a memory controller.
2. The method of claim 1 including providing a register which stores a configuration bit to select one of the first or second modes.
3. The method of claim 2 wherein said first synchronous burst read mode is enabled on the falling ADV# and falling CLK signals.
4. The method of claim 3 wherein addresses are latched on a rising CLK signal with the ADV# signal being low.
5. The method of claim 2 wherein said second synchronous burst mode is enabled on the falling ADV# and rising CLK signals.
6. The method of claim 5 , latching addresses on the rising CLK signal with burst enabled.
7. A memory comprising:
a memory array; and
a device to selectively enable said memory to enter a first synchronous burst read mode or a second synchronous burst read mode based on a signal from a memory controller.
8. The apparatus of claim 7 , said memory including a register to store a configuration bit to select one of said first and second modes.
9. The apparatus of claim 8 wherein said first synchronous burst read mode is enabled on the falling ADV and falling CLK signals.
10. The apparatus of claim 9 wherein addresses are latched on the rising CLK signal with the ADV# signal being low.
11. The apparatus of claim 8 wherein said second synchronous burst mode is enabled on the falling ADV# and rising CLK signals.
12. The apparatus of claim 11 , said device to latch the addresses on the rising CLK signal with burst enabled.
13. A system comprising:
a memory controller; and
a memory coupled to said memory controller, said memory including an array and a device to selectively enable said memory to enter a first synchronous burst read mode or second synchronous burst read mode based on a signal from said memory controller.
14. The system of claim 13 wherein said memory is a flash memory.
15. The system of claim 13 , said memory including a register to store a configuration bit to select one of said first and second modes.
16. The system of claim 15 wherein said first synchronous burst read mode is enabled on the falling ADV# and falling CLK signals.
17. The system of claim 16 wherein addresses are latched on the rising CLK signal with the ADV# signal being low.
18. The system of claim 15 wherein said second synchronous burst mode is enabled on the falling ADV# and rising CLK signals.
19. The system of claim 18 , said device to latch the addresses on the rising CLK signal with burst enabled.
20. The system of claim 15 wherein said bit is supplied by said memory controller.