Password protected built-in test mode for memories
View Patent ↗A semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.
1. An apparatus, comprising:
an integrated semiconductor memory, comprising:
a controller configured to control a built-in test mode;
a memory array coupled to said controller;
random number generator coupled to said controller and configured to provide a random number; and
a test mode decoder coupled to said controller and said random number generator and configured to store a test mode sequence for implementing the built-in test mode and a test mode set-up sequence for configuring a password of the integrated semiconductor memory, said test mode decoder configured to implement a password protection access to said built-in test mode based on the password and the random number.
2. The apparatus of claim 1 wherein said password protected access is selectively implementable.
3. The apparatus of claim 1 wherein said integrated semiconductor memory is a flash memory.
4. The apparatus of claim 1 , wherein the integrated semiconductor memory further comprises a configuration memory configured to store the password, said configuration memory external to said memory array.
5. An apparatus, comprising:
an integrated semiconductor memory device comprising:
a memory array;
a random number generator configured to provide a random number;
a test mode decoder coupled to the random number generator and configured to store a test mode sequence for implementing a built-in test mode and a test mode set-up sequence for configuring a password of the integrated semiconductor memory device, said test mode decoder configured to selectively implement a password protected access to said built-in test mode for said integrated semiconductor memory device using a code derived from the password and the random number.
6. The apparatus of claim 5 , further comprising a configuration memory external from said array to store the password.
7. The apparatus of claim 5 , further comprising a controller configured to control said built-in test mode.
8. The apparatus of claim 5 , further comprising a memory controller coupled to said memory array.
9. The apparatus of claim 8 , wherein said test mode decoder is included in said memory controller.