IP Library Granted Patent US 8,327,087
Granted Patent B1
US 8,327,087 · App. 12/347,962 · Granted Dec 4, 2012

Method and apparatus for an always open write-only register based memory mapped overlay interface for a nonvolatile memory

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Quick Facts
Patent No.
US 8,327,087
App. No.
12/347,962
Granted
Dec 4, 2012
Kind
B1
Abstract

Methods and systems are provided that may include a controller comprising an access element and a command interface. Access element may provide access to a physical nonvolatile memory device. Physical nonvolatile memory device may have a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device. A command interface may modify access to the physical nonvolatile memory device by issuing a command through at least one write overlay window of a memory partition to change the default setting to write to the physical nonvolatile memory. The at least one write overlay window may be logically separate from at least one read overlay window of the memory partition.

Claims (28)

1. A controller, comprising:

an access element to provide access to a physical nonvolatile memory device, the physical nonvolatile memory device having a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device; and

a command interface to modify access to the physical nonvolatile memory device by issuing a command through at least one write overlay window of at least two write overlay windows of a memory partition to change the default setting to write to the physical nonvolatile memory, the at least two write overlay windows being logically separate from at least one read overlay window of the memory partition, wherein the at least two write overlay windows and the at least one read overlay window are capable of being open simultaneously.

2. The controller of claim 1 , wherein the memory partition comprises at least a static random access memory (SRAM).

3. The controller of claim 1 , wherein the controller is in communication with a host device via a random access memory (RAM) bus.

4. The controller of claim 1 , wherein the command interface is adapted to open the at least one read overlay window of the memory partition.

5. The controller of claim 1 , wherein the command interface is adapted to open or close multiple write overlay windows in the memory partition.

6. The controller of claim 1 , wherein the command interface is adapted to control the at least one read overlay window to store at least command response data or status.

7. The controller of claim 1 , wherein the command interface is adapted to preserve the at least one write overlay window in an open state by not closing the at least one write overlay window after a reset operation.

8. The controller of claim 1 , wherein the command interface is adapted to perform one or more physical nonvolatile memory functions or controller-specific functions.

9. A method, comprising:

providing access to a physical nonvolatile memory device, wherein the physical nonvolatile memory device has a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device; and

modifying access to the physical nonvolatile memory device via a command interface by issuing a command through at least one write overlay window of at least two write overlay windows of a memory partition to change the default setting to write to the physical nonvolatile memory, the at least two write overlay windows being logically separate from at least one read overlay window of the memory partition, wherein the at least two write overlay windows and the at least one read overlay window are capable of being open simultaneously.

10. The method of claim 9 , further comprising opening the at least one read overlay window of the memory partition.

11. The method of claim 9 , further comprising opening multiple write overlay windows in the memory partition.

12. The method of claim 9 , further comprising controlling the at least one read overlay window to store at least command response data or status.

13. The method of claim 9 , further comprising preserving the at least one write overlay window in an open state by not closing the at least one write overlay window after a reset operation.

14. The method of claim 9 , further comprising performing one or more physical nonvolatile memory functions or controller-specific functions.

15. A system, comprising:

a memory device comprising a physical nonvolatile memory and a memory partition;

a controller comprising:

an access element to provide access to the physical nonvolatile memory device, the physical nonvolatile memory device having a default setting permitting a direct read operation of the physical nonvolatile memory device while prohibiting a direct write operation of the physical nonvolatile memory device; and

a command interface to modify access to the physical nonvolatile memory device by issuing a command through at least one write overlay window of at least two write overlay windows of a memory partition to change the default setting to write to the physical nonvolatile memory, the at least two write overlay windows being logically separate from at least one read overlay window of the memory partition, wherein the at least two write overlay windows and the at least one read overlay window are capable of being open simultaneously.

16. The system of claim 15 , wherein the memory partition comprises at least a static random access memory (SRAM).

17. The system of claim 15 , wherein the bus comprises a random access memory (RAM) bus.

18. The system of claim 15 , wherein the command interface is adapted to open the at least one read overlay window of the memory partition.

19. The system of claim 15 , wherein the command interface is adapted to open multiple write overlay windows in the memory partition.

20. The system of claim 15 , wherein the command interface is adapted to control the at least one read overlay window to store at least command response data or status.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2010
From: AHLQUIST, BRENT
To: NUMONYX B.V.
Reel/Frame 024760/0592 →