IP Library Granted Patent US 8,531,849
Granted Patent B1
US 8,531,849 · App. 12/751,695 · Granted Sep 10, 2013

Supply voltage or ground connections including bond pad interconnects for integrated circuit device

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Quick Facts
Patent No.
US 8,531,849
App. No.
12/751,695
Granted
Sep 10, 2013
Kind
B1
Abstract

Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects.

Claims (39)

1. An integrated circuit device, comprising:

an integrated circuit die comprising a plurality of supply voltage bond pads;

one or more supply voltage bond pad interconnects, each supply voltage bond pad interconnect electrically connected to two or more of the plurality of supply voltage bond pads;

a substrate having a plurality of supply voltage bond fingers individually electrically connected to one or more of the plurality of supply voltage bond pads via one or more supply voltage bond interconnects; and

one or more supply voltage bond finger interconnects, each supply voltage bond finger interconnect electrically interconnecting two or more of the plurality of supply voltage bond fingers.

2. The integrated circuit device of claim 1 , wherein the plurality of supply voltage bond pads individually comprise a primary bond pad area and a supplemental bond pad area, wherein the one or more supply voltage bond interconnects are connected between the one or more of the plurality of supply voltage bond fingers and one or more primary bond pad areas of the supply voltage bond pads, and wherein one or more supply voltage bond pad interconnects are electrically connected to the supplemental bond pad areas of two or more of the plurality of supply voltage bond pads.

3. The integrated circuit device of claim 2 , further comprising a plurality of solder balls positioned on, over, or in a second surface of the substrate, wherein the integrated circuit and the plurality of bond fingers are positioned on, over, or in a first surface of said substrate, wherein the plurality of solder balls are individually electrically coupled to one or more of the plurality of supply voltage bond fingers through one or more electrically conductive traces or electrically conductive vias extending from the first surface to the second surface of the substrate, wherein two or more of the plurality of solder balls are electrically interconnected via an electrically conductive interconnect.

4. The integrated circuit device of claim 1 , wherein the integrated circuit die further comprises a plurality of ground voltage bond pads, and wherein said first surface of the substrate further has positioned thereon, there above, or therein, a plurality of ground voltage bond fingers individually connected to two or more of the plurality of ground voltage bond pads via one or more ground voltage bond interconnects.

5. The integrated circuit device of claim 4 , further comprising one or more ground voltage bond pad interconnects, each ground bond pad interconnect electrically connected to two or more of the plurality of ground voltage bond pads.

6. The integrated circuit device of claim 1 , wherein the supply voltage bond pads comprise first supply voltage bond pads, the supply voltage bond fingers comprise first supply voltage bond fingers, said supply voltage bond interconnects comprise first supply voltage bond interconnects, and said supply voltage bond pad interconnects comprise first supply voltage bond pad interconnects, wherein the integrated circuit die further comprises a plurality of second supply voltage bond pads, and wherein said substrate further has positioned thereon, there above, or therein, a plurality of second supply voltage bond fingers individually connected to two or more of the plurality of second supply voltage bond pads via one or more second supply voltage bond interconnects.

7. The integrated circuit device of claim 5 , further comprising one or more second supply voltage bond pad interconnects, each second supply voltage bond pad interconnect electrically connected to two or more of the plurality of second supply voltage bond pads.

8. A method, comprising:

electrically connecting a plurality of supply voltage bond pads of an integrated circuit to a respective plurality of supply voltage bond fingers positioned on, over, or in a first surface of a substrate;

electrically interconnecting two or more of the plurality of supply voltage bond pads, wherein the supply voltage bond pads are electrically interconnected by one or more supply voltage bond pad interconnects; and

electrically interconnecting two or more of the plurality of supply voltage bond fingers, wherein the supply voltage bond fingers are electrically interconnected by one or more supply voltage bond finger interconnects.

9. The method of claim 8 , further comprising electrically connecting a plurality of solder balls to one or more of the plurality of supply voltage bond fingers.

10. The method of claim 9 , further comprising:

electrically connecting two or more of the plurality of solder fingers via one or more electrically conductive interconnects positioned on, over, or in the first surface of the substrate; and

electrically connecting two or more of the plurality of solder balls via one or more electrically conductive interconnects positioned on, over, or in the second surface of the substrate.

11. The method of claim 8 , further comprising:

electrically connecting a plurality of ground voltage bond pads of the integrated circuit to a respective plurality of ground voltage bond fingers positioned on, over, or in the first surface of the substrate; and

electrically interconnecting two or more of said plurality of ground voltage bond pads.

12. The method of claim 8 , wherein the supply voltage bond pads comprise first supply voltage bond pads, the supply voltage bond fingers comprise first supply voltage bond fingers, the supply voltage bond wires comprise first supply voltage bond wires, and the supply voltage bond pad interconnects comprise first supply voltage bond pad interconnects, and wherein the method further comprises:

electrically connecting a plurality of second supply voltage bond pads of the integrated circuit to a respective plurality of second supply voltage bond fingers positioned on, over, or in the first surface of the substrate; and

electrically interconnecting two or more of the plurality of second supply voltage bond pads via one or more second supply voltage bond pad interconnects.

13. A system, comprising:

a power supply to generate a first supply voltage;

a processor; and

a memory device coupled to the processor, the memory device to receive the first supply voltage from the power supply, the memory device comprising

an integrated circuit die comprising a plurality of first supply voltage bond pads;

one or more first supply voltage bond pad interconnects, each supply voltage bond pad interconnect electrically connected to two or more of the plurality of first supply voltage bond pads;

a substrate having positioned thereon, there above, or therein, a plurality of first supply voltage bond fingers individually electrically connected to one or more of the plurality of first supply voltage bond pads via one or more first supply voltage bond interconnects; and

one or more first supply voltage bond finger interconnects, each supply voltage bond finger interconnect electrically interconnecting two or more of the plurality of first supply voltage bond fingers.

14. The system of claim 13 , wherein the substrate comprises a first and a second surface, wherein the second surface of the substrate has positioned thereon, there above, or therein, a plurality of solder balls to receive said first supply voltage from the power supply, the plurality of solder balls individually electrically connected to one or more of the plurality of first supply voltage bond fingers.

15. The system of claim 14 , wherein two or more of the plurality of solder balls are electrically connected via one or more electrically conductive interconnects formed on, over, or in one or more of the first and second surfaces of the substrate, and wherein two or more of the plurality of first supply voltage bond fingers are electrically connected via one or more first supply voltage bond finger interconnects.

16. The system of claim 13 , wherein the integrated circuit die further comprises a plurality of ground voltage bond pads, and wherein the first surface of the substrate further has positioned thereon, there above, or therein, a plurality of ground voltage bond fingers individually connected to one or more of the plurality of ground voltage bond pads via one or more ground voltage bond interconnects.

17. The system of claim 16 , wherein the memory device further comprises one or more ground voltage bond pad interconnects, each ground voltage bond pad interconnect electrically connected to two or more of the plurality of ground voltage bond pads.

18. The system of claim 13 , the power supply further to generate a second supply voltage, wherein the integrated circuit die further comprises a plurality of second supply voltage bond pads, and wherein the substrate further has positioned thereon, there above, or therein, a plurality of second supply voltage bond fingers individually electrically connected to one or more of the plurality of second supply voltage bond pads via one or more second supply voltage bond interconnects.

19. The system of claim 18 , the memory device further comprising one or more second supply voltage bond pad interconnects, each second supply voltage bond pad interconnect electrically connected to two or more of the plurality of second supply voltage bond pads.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2010
From: ABDULLA, MOSTAFA NAGUIB; ESKILDSEN, STEVEN
To: NUMONYX B.V.
Reel/Frame 024757/0014 →