Wordline driver for memory
View Patent ↗Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.
1. A memory device comprising:
memory cells of a memory cell array which are addressable via a wordline;
a pull-up-pull-down (PUPD) string to select or deselect said wordline, said PUPD string comprising:
pull-down transistors electrically connected between said wordline and a current sink to select said wordline; and
one or more pull-up resistors electrically connected between said wordline and a voltage source to deselect said wordline, wherein said one or more pull-up resistors are serially connected to said pull-down transistors, and
an additional transistor to inject electrical current into said PUPD string between a consecutive two of said pull-down transistors to deselect said wordline at a rate faster than deselection of said wordline performed without said injected electrical current.
2. The memory device of claim 1 , wherein said one or more pull-up resistors comprise silicon diffusion on or near an edge of said memory cell array.
3. The memory device of claim 2 , wherein said silicon diffusion comprises an n-type material implanted in a silicon substrate.
4. The memory device of claim 1 , wherein said one or more pull-up resistors comprise silicon diffusion on or near a beginning of said word line that extends to bases of said memory cells.
5. The memory device of claim 1 , further comprising an inverter electrically connected between a base of one of said consecutive two pull-down transistors and a base of said additional transistor.
6. The memory device of claim 1 , wherein said pull-down transistors comprise NMOS transistors.
7. A method comprising:
forming a wordline on a substrate to address memory cells of a memory cell array; and
forming one or more pull-up resistors on said substrate, said one or more pull-up resistors to raise a voltage to deselect said wordline; and
forming a transistor to inject electrical current between two consecutive pull-down transistors serially connected to said one or more pull-up resistors to deselect said wordline at a rate faster than deselection of said wordline performed without said injected electrical current.
8. The method of claim 7 , further comprising
forming said memory cell array and said one or more pull-up resistors at substantially the same time using a same mask.
9. The method of claim 7 , wherein said one or more pull-up resistors are formed using silicon diffusion.
10. The method of claim 9 , wherein said silicon diffusion comprises an n-type material implanted in said substrate.
11. The method of claim 10 , wherein an edge of said memory cell array comprises a beginning of said word line that extends to bases of said memory cells.
12. The method of claim 7 , further comprising:
forming an inverter to electrically connect a base of one of said two consecutive pull-down transistors and a base of said additional transistor.
13. The method of claim 7 , wherein said two consecutive pull-down transistors comprise an NMOS transistor.
14. A system comprising:
a memory controller to operate a memory device, said memory device comprising:
memory cells of a memory cell array which are addressable via a wordline;
a pull-up-pull-down (PUPD) string to select or deselect said wordline responsive to electronic signals generated by decoding a command, wherein said PUPD includes one or more pull-up resistors electrically connected between said wordline and a voltage source to deselect said wordline;
pull-down transistors serially connected to said one or more pull-up resistors in said PUPD string and electrically connected between said wordline and a current sink to select said wordline; and
an additional transistor to inject electrical current into said PUPD string between a consecutive two of said pull-down transistors to deselect said wordline at a rate faster than deselection of said wordline performed without said injected electrical current; and
a processor to host one or more applications and to initiate said command to said memory controller to provide access to said memory cells in said memory cell array.
15. The system of claim 14 , wherein said pull-down transistors comprise NMOS transistors.
16. The system of claim 14 , wherein said one or more pull-up resistors comprise silicon diffusion on or near an edge of said memory cell array.