IP Library Granted Patent US 9,093,266
Granted Patent B2
US 9,093,266 · App. 13/083,836 · Granted Jul 28, 2015

Forming high aspect ratio isolation structures

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Quick Facts
Patent No.
US 9,093,266
App. No.
13/083,836
Granted
Jul 28, 2015
Kind
B2
Abstract

An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture with boron. In some embodiments, the aperture filling may use atomic layer deposition. In some cases, the boron may be amorphous boron. The aperture may be a high aspect ratio aperture, such as a trench, in some embodiments.

Claims (29)

1. A method comprising:

forming an electrically isolating aperture in a semiconductor substrate; and

filling the aperture with a material consisting essentially of amorphous boron.

2. The method of claim 1 including using atomic layer deposition to fill the aperture with amorphous boron.

3. The method of claim 1 including forming a high aspect ratio aperture in said semiconductor substrate.

4. The method of claim 1 wherein forming an aperture includes forming a trench.

5. The method of claim 1 wherein filling the aperture includes forming a trench isolation.

6. A semiconductor device comprising:

a substrate; and

a filled isolation structure including a high aspect ratio aperture in said substrate, said aperture filled with a material consisting essentially of amorphous boron and configured to electrically isolate a first area from a second area of said semiconductor device.

7. The device of claim 6 wherein said aperture is a trench.

8. The device of claim 6 wherein said substrate is a semiconductor substrate.

9. The device of claim 6 wherein said device is a flash memory.

10. A method comprising:

forming an electrical isolation trench in a semiconductor substrate; and

using atomic layer deposition to fill said electrical isolation trench with a material consisting essentially of amorphous boron to form an isolation structure.

11. The method of claim 10 including using atomic layer deposition to fill the trench with amorphous boron.

12. A memory comprising:

a semiconductor substrate;

a high aspect ratio trench electrical isolation structure filled with a material consisting essentially of amorphous boron in said semiconductor substrate; and

memory devices formed in said semiconductor substrate.

13. The memory of claim 12 wherein said trench has an aspect ratio of greater than ten.

14. The memory of claim 12 wherein said memory is a flash memory.

15. The method of claim 1 wherein filling the aperture with amorphous boron comprises exposing the aperture to a flow of diborane.

16. The method of claim 1 wherein filling the aperture with amorphous boron comprises depositing a monolayer of amorphous boron in the aperture.

17. The method of claim 1 wherein filling the aperture with amorphous boron comprises filling the aperture monolayer by monolayer.

18. The semiconductor device of claim 6 wherein the boron comprises a continuous layer of amorphous boron.

19. The method of claim 10 wherein using atomic layer deposition to fill said trench comprises forming a monolayer of amorphous boron on said trench.

20. The memory of claim 12 wherein the amorphous boron comprises a continuous layer of amorphous boron.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2011
From: BORSARI, SILVIA; LAZZARI, CARLA MARIA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026104/0709 →