Memory apparatus and system with shared wordline decoder
View Patent ↗A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
1. A memory device comprising:
two memory blocks, each including wordlines; and
a decoder circuit positioned between the two memory blocks including a first level decoder coupled to the wordlines in the two memory blocks and a shared second level decoder coupled to the first level decoder, the first level decoder including a first section coupled to one half of the wordlines in a first of the two memory blocks and configured to drive the one half of the word lines in the first of the two memory blocks, and the first level decoder further including a second section coupled to one half of the wordlines in the second of the two memory blocks and configured to drive the one half of the wordlines in the second of the two memory blocks.
2. The memory device of claim 1 wherein the decoder circuit is coupled to every other wordline in the first of the two memory blocks and to every other wordline in the second of the two memory blocks.
3. The memory device of claim 1 wherein the decoder circuit further comprises a shared third level coupled to the shared second level decoder.
4. The memory device of claim 1 further comprising a first pre-decoder circuit coupled to pre-decode a first subset of address lines and to drive the first level decoder of the decoder circuit.
5. The memory device of claim 4 further comprising a second pre-decoder circuit coupled to pre-decode a second subset of address lines and to drive the shared second level of the decoder circuit.
6. The memory device of claim 5 further comprising:
a shared third level within the decoder circuit coupled to the shared second level; and
a third pre-decoder circuit coupled to pre-decode a third subset of address lines and to drive the shared third level of the decoder circuit.
7. A memory device comprising:
a plurality of memory blocks; and
a plurality of multi-level shared wordline decoders, each of the plurality of multi-level shared wordline decoders including a split first level and a shared second level, the split first level being split into two sections, the two sections including selection transistors coupled to wordlines in different ones of the plurality of memory blocks, and the shared second level being coupled in common to the two sections of the split first level.
8. The memory device of claim 7 wherein the plurality of memory blocks are arranged in rows, and each of the plurality of multi-level shared wordline decoders is positioned between memory blocks in a row.
9. The memory device of claim 8 wherein each of the plurality of multi-level shared wordline decoders is coupled to wordlines in adjacent memory blocks.
10. The memory device of claim 8 wherein each of the plurality of memory blocks has even wordlines coupled to one multi-level shared wordline decoder on a first side and odd wordlines coupled to another multi-level shared wordline decoder on a second side.
11. The memory device of claim 7 further comprising a plurality of pre-decoders to separately enable the split first level and shared second level of the multi-level shared wordline decoders.
12. An electronic system comprising:
a wireless interface;
a processor coupled to the wireless interface; and
a memory device having at least two memory blocks, each including wordlines, and a decoder circuit positioned between the two memory blocks including a first level decoder coupled to the wordlines in the two memory blocks and a shared second level decoder coupled to the first level decoder, the first level decoder including a first section coupled to one half of the wordlines in a first of the two memory blocks and configured to drive the one half of the word lines in the first of the two memory blocks, and the first level decoder further including a second section coupled to one half of the wordlines in the second of the two memory blocks and configured to drive the one half of the word lines in the second of the two memory blocks.
13. The electronic system of claim 12 wherein the decoder circuit is coupled to every other wordline in a first of the two memory blocks and to every other wordline in a second of the two memory blocks.
14. The electronic system of claim 12 wherein the decoder circuit further comprises a shared third level coupled to the shared second level.
15. The electronic system of claim 12 further comprising a plurality of pre-decoders to separately enable the first level decoder and the shared second level decoder of the decoder circuit.
16. A method comprising:
partially decoding a first subset of address lines in a memory device and driving a split first level decoder that selects wordlines in one of two memory blocks and that does not select a wordline in another of the two memory blocks; and
partially decoding a second subset of address lines in the memory device and driving a second decoder that enables the split first level decoder.
17. The method of claim 16 wherein driving a split first level decoder that selects wordlines in one of two memory blocks comprises driving a split first level decoder that is coupled to every other wordline in a first memory block and every other wordline in a second memory block.
18. The method of claim 16 further comprising partially decoding a third subset of address lines in the memory device and driving a third decoder that enables the second decoder.