Method of fabricating a charge trap NAND flash memory
View Patent ↗Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.
1. A method of fabricating a charge trap NAND memory device, the method comprising:
forming a recessed silicon region in a circuitry region of a semiconductor substrate, wherein a height of said recessed silicon region is less than a height of an array region of said semiconductor substrate;
after forming said recessed silicon region in said circuitry region:
forming trenches in said recessed silicon region; and
filling said trenches with an insulating material, and planarizing a resultant structure to form shallow trench isolation (STI) structures to define one or more wells, low voltage (LV) gate oxides, and high voltage (HV) gate oxides in said recessed silicon region;
forming an isolated p-well in an array region of said semiconductor substrate; and
forming a tunnel oxide on said array region.
2. The method of claim 1 , further comprising:
forming a charge trap layer on said tunnel oxide.
3. The method of claim 2 , further comprising:
forming a high-k layer on said charge trap layer;
forming a polysilicon layer over said LV gate oxide and said HV gate oxide; and
forming a metal gate layer on said high-k layer in said array region and on said polysilicon layer in said circuitry region.
4. The method of claim 3 , further comprising:
forming an oxide hard mask layer on said metal gate layer; and
patterning said metal gate layer using said hard mask layer to form periphery gates and a local interconnection between said array region and said circuitry region.
5. The method of claim 4 , wherein forming said oxide hard mask layer on said metal gate layer in said array region and forming said oxide hard mask layer on said metal gate layer in said circuitry region are performed at different times.
6. The method of claim 5 , further comprising selectively etching said oxide hard mask layer, wherein selectively etching said oxide hard mask layer in said array region and selectively etching said oxide hard mask layer in said circuitry region are performed at different times.
7. The method of claim 3 , further comprising:
forming a first oxide hard mask layer on said metal gate layer in said array region; and
forming a second oxide hard mask layer on said metal gate layer in said circuitry region, wherein forming said first oxide hard mask layer and forming said second oxide hard mask layer are performed at different times.
8. The method of claim 6 , further comprising:
selectively etching said first oxide hard mask layer in said array region; and
selectively etching said second oxide hard mask layer in said circuitry region, wherein selectively etching said first oxide hard mask layer and selectively etching said second oxide hard mask layer are performed at different times.
9. The method of claim 8 , further comprising:
forming a first pre-metal dielectric in said array region; and
forming a second pre-metal dielectric in said circuitry region, wherein forming said first pre-metal dielectric and forming said second pre-metal dielectric are performed at different times.
10. The method of claim 1 , further comprising:
forming a metal gate layer in said array region and in said recessed silicon region, wherein said metal gate layer is common for both said array region and said recessed silicon region;
masking a portion of said metal gate layer in said recessed silicon region to form a patterned metal gate layer; and
electrically interconnecting said array region with said recessed silicon region using said metal gate layer.
11. A method of manufacturing a semiconductor integrated circuit memory structure, the method comprising:
forming a recessed silicon region in a peripheral region of a semiconductor substrate, wherein a height of said recessed silicon region is less than a height of an array region of said semiconductor substrate;
after forming said recessed silicon region in said circuitry region:
forming a metal gate layer common to said array region and said recessed silicon region of said memory structure; and
masking a portion of said metal gate layer in said recessed silicon region to form a patterned metal layer; and
electrically interconnecting said array region with said recessed silicon region using said metal gate layer, wherein said array region is formed by a lithography process different than that of said recessed silicon region.
12. The method of claim 11 , wherein said memory structure comprises a charge trap NAND flash memory structure.
13. The method of claim 11 , wherein said array region comprises word and/or bit lines.
14. The method of claim 11 , further comprising:
forming a first pre-metal dielectric in said array region; and
forming a second pre-metal dielectric in said peripheral region, wherein forming said first pre-metal dielectric and forming said second pre-metal dielectric are performed at different times.
15. The method of claim 14 , wherein said array region and said peripheral region comprise materials that are substantially different from one another.
16. The method of claim 11 , further comprising:
forming one or more wells and/or active gate oxides in said peripheral region, wherein said one or more wells and/or active gate oxides include an LV oxide and/or an HV oxide.
17. The method of claim 11 , further comprising:
forming a first metal gate layer in said array region; and
forming a second metal gate layer in said peripheral region, wherein said first metal gate layer and second metal gate layer comprise substantially the same material composition.
18. The method of claim 17 , wherein said first metal gate layer comprises a source connection to said array region.
19. The method of claim 17 , wherein said first metal gate layer comprises a connection between word lines and said array region.