IP Library Granted Patent US 8,236,691
Granted Patent B2
US 8,236,691 · App. 12/347,721 · Granted Aug 7, 2012

Method of high aspect ratio plug fill

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Quick Facts
Patent No.
US 8,236,691
App. No.
12/347,721
Granted
Aug 7, 2012
Kind
B2
Abstract

A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.

Claims (11)

1. A method comprising:

forming a dielectric layer on a semiconductor containing layer;

forming a via in the dielectric layer, the via extending to the semiconductor containing layer such that a bottom surface of the via is a portion of the semiconductor containing layer;

utilizing a one directional collimated sputtering deposition technique, depositing a nucleation layer on only the bottom surface of the via and not on sidewalls of the via; and

utilizing a chemical vapor deposition (CVD) technique, depositing a conductive fill material on the nucleation layer up to a top of the via to create a seamless plug fill, the conductive fill material being grown from the bottom up and not inward from the sidewalls and filling a bulk of the via.

2. The method of claim 1 , wherein the nucleation layer comprises at least one conductive material selected from a group consisting of metal, silicide, boride, and nitride.

3. The method of claim 1 , wherein the nucleation layer comprises titanium.

4. The method of claim 1 , wherein a height of the via is at least 10 times a width of the via.

5. The method of claim 1 , wherein the conductive fill material deposited on the nucleation layer comprises at least one conductive material selected from a group consisting of titanium, tungsten, and their alloys.

6. The method of claim 1 , wherein the CVD technique is selected from the group consisting of CVD, MOCVD, and PECVD.

7. The method of claim 1 , wherein the forming of the via is performed by etching.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2010
From: SHOR, YAKOV; ALTSHULER, SEMEON; ROTLAIN, MAOR; ALON, YIGAL; HORVITZ, DROR
To: NUMONYX B.V.
Reel/Frame 024597/0818 →