IP Library Granted Patent US 8,307,151
Granted Patent B1
US 8,307,151 · App. 12/628,152 · Granted Nov 6, 2012

Multi-partitioning feature on e-MMC

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Quick Facts
Patent No.
US 8,307,151
App. No.
12/628,152
Granted
Nov 6, 2012
Kind
B1
Abstract

An e-MMC memory having a controller for a NAND Flash and another controller for a Phase-Change Memory (PCM) in a memory managed system. The different memory technologies of the NAND Flash and PCM may be partitioned to segment available memory space to store different types of data or code while accounting for an attribute property stored in a register.

Claims (43)

1. An embedded multi-media card (e-MMC) memory to couple to a host, the e-MMC memory comprising:

a first interface controller and a second interface controller, the first interface controller configured to be aware of the existence of the second interface controller and the second interface controller configured not to be aware of the first interface controller; and

a NAND Flash coupled to the first interface controller and a Phase-Change Memory (PCM) coupled to the second interface controller to reconfigure partitions according to the host.

2. The e-MMC memory of claim 1 wherein the first interface controller and the second interface controller both include a registers management block to track memory partitions which are enabled to map memory partitions.

3. The e-MMC memory of claim 1 wherein the first interface controller is configured to manage commands to mapped portions of the NAND Flash without an attribute enhanced set and the second interface controller is to map the portions of the Phase-Change Memory with the attribute enhanced set.

4. The e-MMC memory of claim 1 , wherein during a power management mode both the first interface controller and the second interface controller are to execute state transitions to an inactive state and only the first interface controller is to reply to the host.

5. The e-MMC memory of claim 1 , where a register is to inhibit a response in the second interface controller while the first interface controller is configured to be in charge of generating the response to the host.

6. The e-MMC memory of claim 1 , wherein reconfiguring the PCM to change memory partitions is not a One Time Programmable operation.

7. The e-MMC memory of claim 6 , wherein there is no degradation of the storage media due to the reconfiguration process and reconfiguring is done during a lifecycle of the e-MMC memory.

8. An embedded multi-media card (e-MMC) memory, comprising:

a NAND Flash coupled to a first interface controller; and

a Phase-Change Memory (PCM) coupled to a second interface controller to manage commands referencing partitions set up in the e-MMC memory using a connection between the first interface controller and the second interface controller, the first interface controller being configured to manage up to four General Purpose Partitions if a partition has an enhanced attribute reset.

9. The e-MMC memory of claim 8 , wherein the connection is to allow commands and data to be received and data to be sent from the PCM as requested by the host.

10. The e-MMC memory of claim 8 , wherein the second interface controller is to handle the partitioning if the partition has an enhanced attribute set.

11. The e-MMC memory of claim 8 , wherein the second interface controller is to handle two boot areas and a Replay Protected Memory Block (RPMB) partition area.

12. The e-MMC memory of claim 8 , wherein the first interface controller handles an Enhanced User Data Area (EUDA) if it is implemented by a MLC NAND Flash settable as SLC.

13. A Phase-Change Memory (PCM) and a Multi-Level Cell (MLC) NAND Flash in a managed memory having an attribute property, the PCM and the MLC NAND Flash comprising:

embedded multi-media card (e-MMC) bus terminals;

a first controller coupled to the e-MMC bus terminals and coupled to the MLC NAND Flash; and

a second controller coupled to the PCM, a combination of the MLC NAND Flash and the PCM is to differentiate memory portions in which the attribute property is set, the first controller configured to be aware of the existence of the second controller and the second controller configured not to be aware of the first controller.

14. The PCM and MLC NAND Flash of claim 13 wherein the first controller is to service requests to access a User Data Area, an Enhanced User Data Area, and all General Purpose Partitions where the attribute property is not set.

15. An embedded multi-media card (e-MMC) memory to couple to a host, the e-MMC memory comprising:

a first interface controller and a second interface controller; and

a NAND Flash coupled to the first interface controller and a Phase-Change Memory (PCM) coupled to the second interface controller to reconfigure partitions as directed by the host, the first interface controller being configured to manage commands to mapped portions of the NAND Flash without an attribute enhanced set and the second interface controller being configured to map the portions of the Phase-Change Memory with the attribute enhanced set.

16. An embedded multi-media card (e-MMC) memory to couple to a host, the e-MMC memory comprising:

a first interface controller and a second interface controller;

a NAND Flash coupled to the first interface controller and a Phase-Change Memory (PCM) coupled to the second interface controller to reconfigure partitions as directed by the host; and

a register to inhibit a response in the second interface controller while the first interface controller is configured to manage generating the response to the host.

17. An embedded multi-media card (e-MMC) memory, comprising:

a NAND Flash coupled to a first interface controller; and

a Phase-Change Memory (PCM) coupled to a second interface controller to manage commands referencing partitions set up in the e-MMC memory using a connection between the first interface controller and the second interface controller, the second interface controller being configured to handle partitioning if the partition has an enhanced attribute set.

18. An embedded multi-media card (e-MMC) memory, comprising:

a NAND Flash coupled to a first interface controller; and

a Phase-Change Memory (PCM) coupled to a second interface controller to manage commands referencing partitions set up in the e-MMC memory using a connection between the first interface controller and the second interface controller, the first interface controller configured to be aware of the existence of the second interface controller and the second interface controller configured not to be aware of the first interface controller.

19. A Phase-Change Memory (PCM) and a Multi-Level Cell (MLC) NAND Flash in a managed memory having an attribute property, the PCM and the MLC NAND Flash comprising:

embedded multi-media card (e-MMC) bus terminals;

a first controller coupled to the e-MMC bus terminals and coupled to the MLC NAND Flash; and

a second controller coupled to the PCM, a combination of the MLC NAND Flash and the PCM is to differentiate memory portions in which an attribute property is set, the first controller being configured to manage commands to mapped portions of the MLC NAND Flash without an attribute enhanced set and the second controller being configured to map the portions of the PCM with the attribute enhanced set.

20. A Phase-Change Memory (PCM) and a Multi-Level Cell (MLC) NAND Flash in a managed memory having an attribute property, the PCM and the MLC NAND Flash comprising:

embedded multi-media card (e-MMC) bus terminals;

a first controller coupled to the e-MMC bus terminals and coupled to the MLC NAND Flash;

a second controller coupled to the PCM, a combination of the MLC NAND Flash and the PCM is to differentiate memory portions in which an attribute property is set; and

a register to inhibit a response in the second controller while the first controller is configured to be in charge of generating the response to a host.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2010
From: CARACCIO, DANILO; CONFALONIERI, EMANUELE; TIZIANI, FEDERICO
To: NUMONYX B.V.
Reel/Frame 024709/0857 →