Method for fabricating a phase-change memory cell
A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer ( 228 ) on a metal layer ( 226 ) above a substrate. A phase-change material layer ( 230 ) is formed on the dielectric layer. A contact region ( 232 ) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.
1. A method of fabricating a phase-change memory cell, the method comprising:
forming a dielectric layer on a metal layer above a substrate;
forming a phase-change material layer on the dielectric layer; and
forming, within the dielectric layer, a contact region between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer, the forming of the contact region including
determining a set-state target current for the phase-change material layer; and
applying, through the metal layer, a current pulse greater than the set-state target current; and
subsequent to applying the current pulse greater than the set-state target current, making a determination of an actual amount of current driven by the phase-change memory cell in a crystalline state; and,
based on a determination that the actual amount of current is less than the set-state target current, applying a second current pulse greater than the set-state target current, an amplitude of the second current pulse being greater than an amplitude of the current pulse; and
subsequent to applying the second current pulse, making another determination of the actual current driven by the phase-change memory cell in the crystalline state.
2. The method of claim 1 , wherein the set-state target current is approximately 10 micro-Amps, and wherein the current pulse greater than the set-state target current is approximately in the range of 50 micro-Amps to 100 micro-Amps.
3. The method of claim 1 , wherein applying the current pulse greater than the set-state target current comprises applying a current pulse having a falling edge with a duration approximately in the range of 100 nanoseconds to 1000 nanoseconds.
4. The method of claim 3 , wherein, subsequent to applying the current pulse, the phase-change memory cell is in a crystalline state.
5. The method of claim 1 , wherein the method further comprises repeating the applying and determining steps until the phase-change memory cell exhibits the set-state target current.
6. The method of claim 1 , wherein forming the dielectric layer on the metal layer above the substrate comprises forming the dielectric layer above a heater element.
7. The method of claim 6 , wherein forming the dielectric layer above the heater element comprises forming the dielectric layer above a heater element having a vertical wall configuration.
8. The method of claim 1 , wherein forming the dielectric layer on the metal layer above the substrate comprises forming the dielectric layer above a metal plug.
9. The method of claim 1 , wherein forming the phase-change material layer on the dielectric layer comprises forming a layer of Ge 2 Sb 2 Te 5 on the dielectric layer.
10. The method of claim 1 , wherein forming the dielectric layer on the metal layer above the substrate comprises forming an oxygen-free layer by a chemical vapor deposition process.
11. The method of claim 10 , wherein forming the oxygen-free layer comprises forming a silicon nitride layer by a chemical vapor deposition process.
12. The method of claim 11 , wherein forming the silicon nitride layer comprises forming a silicon nitride thickness approximately in the range of 1 nanometer to 2 nanometers.
13. The method of claim 1 , wherein forming the contact region between the phase-change material layer and the metal layer and within the dielectric layer comprises forming a contact region having approximately vertical sidewalls.