Multilevel encoding with error correction
View Patent ↗Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.
1. A method of encoding a plurality of bits into a plurality of multilevel memory cells comprising:
level-shifting a first subset of the plurality of multilevel memory cells to encode a first bit of the plurality of bits and a second subset of the plurality of multilevel memory cells to encode a second bit of the plurality of bits, wherein one of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit and by the encoding of the second bit, and another of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit, but not by the encoding of the second bit.
2. The method of claim 1 , wherein two or more of the plurality of multilevel memory cells are associated with a respective subset, which includes at least one other multilevel memory cell, that is used to encode a respective bit.
3. The method of claim 1 , further comprising: controlling the plurality of multilevel memory cells to maintain a Hamming distance between states of the plurality of multilevel memory cells.
4. The method of claim 1 , wherein the encoding further comprises: level-shifting a third subset of the plurality of multilevel memory cells to encode a third bit of the plurality of bits, wherein yet another of the plurality of multilevel memory cells is level-shifted by the encoding of the second bit and by the encoding of the third bit, and still another of the plurality of multilevel memory cells is level-shifted by the encoding of the second bit, but not by the encoding of the third bit.
5. The method of claim 1 further comprising: level-shifting a multilevel memory cell two or more levels to encode two or more bits.
6. A method comprising:
receiving input data represented as a plurality of bits;
encoding the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells; and
controlling the plurality of multilevel memory cells in a manner to maintain a predetermined threshold Hamming distance between states of the plurality of multilevel memory cells, the states of the plurality of multilevel cells respectively corresponding to values of the plurality of bits, wherein said controlling comprises:
detecting a predetermined value of the first plurality of bits; and level-shifting one or more of the plurality of multilevel memory cells, based at least in part on said detecting of the predetermined value.
7. A method comprising: receiving input data represented as a plurality of bits; and encoding the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells, and wherein the plurality of multilevel memory cells is M, each of the plurality of multilevel memory cells can be level-shifted a total of L times before being erased, the plurality of bits is B, a desired Hamming distance is H, and M, L, B, and H satisfy (M*L)>(B*H).
8. An apparatus comprising: a plurality of multilevel memory cells and a device capable of encoding a plurality of bits in the plurality of multilevel memory cells by:
level-shifting a first subset of the plurality of multilevel memory cells to encode a first bit of the plurality of bits, and a second subset of the plurality of multilevel memory cells to encode a second bit of the plurality of bits, wherein one of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit and by the encoding of the second bit, and another of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit, but not by the encoding of the second bit.
9. The apparatus of claim 8 , wherein the device is further capable of controlling the plurality of multilevel memory cells to maintain a Hamming distance between states of the plurality of multilevel memory cells.
10. The apparatus of claim 8 , wherein the device is further capable of level-shifting a third subset of the plurality of multilevel memory cells to encode a third bit of the plurality of bits wherein yet another of the multilevel memory cells is level-shifted by the encoding of the second bit and by the encoding of the third bit, and still another of the multilevel memory cells is level-shifted by the encoding of the second bit, but not by the encoding of the third bit.
11. The apparatus of claim 8 , wherein the device is further capable of level-shifting a multilevel memory cell of the plurality of multilevel memory cells two or more levels to encode two or more bits of the plurality of bits.
12. An apparatus comprising: a matrix of memory cells; and a programmer coupled to the matrix of memory cells and configured to receive input data represented as a plurality of bits, and to encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits,
wherein the subset includes two or more multilevel memory cells, and
wherein the programmer is further configured to control the plurality of multilevel memory cells in a manner to maintain a predetermined threshold Hamming distance between states of the plurality of multilevel memory cells, the states of the plurality of multilevel cells respectively corresponding to values of the plurality of bits, and
wherein the programmer is further configured to control the plurality of multilevel memory cells by being configured to: detect a predetermined value of the first plurality of bits; and level-shift one or more of the plurality of multilevel memory cells based at least in part on detection of the predetermined value.
13. An apparatus comprising: a matrix of memory cells; and a programmer coupled to the matrix of memory cells and configured to receive input data represented as a plurality of bits, and to encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells, wherein the plurality of multilevel memory cells is M, each of the plurality of multilevel memory cells can be level-shifted a total of L times before being erased, the plurality of bits is B, a desired Hamming distance is H, and M, L, B, and H satisfy (M*L)>(B*H).
14. An apparatus comprising: memory having instructions that, when executed, cause the apparatus to encode a plurality of bits into a plurality of multilevel memory cells by level-shifting a first subset of the plurality of multilevel memory cells to encode a first bit of the plurality of bits, and
a second subset of the plurality of multilevel memory cells to encode a second bit of the plurality of bits, wherein one of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit and by the encoding of the second bit, and another of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit, but not by the encoding of the second bit.
15. The apparatus of claim 14 , wherein two or more of the plurality of multilevel memory cells are associated with a respective subset, which includes at least one other multilevel memory cell, that is used to encode a respective bit.
16. The apparatus of claim 14 , wherein the instructions, when executed, further cause the apparatus to: control the plurality of multilevel memory cells to maintain a Hamming distance between states of the plurality of multilevel memory cells.
17. The apparatus of claim 14 , wherein the instructions further cause the apparatus to: level-shift a third subset of the plurality of multilevel memory cells to encode a third bit of the plurality of bits, wherein yet another of the plurality of multilevel memory cells is level-shifted by the encoding of the second bit and by the encoding of the third bit, and still another of the plurality of multilevel memory cells is level-shifted by the encoding of the second bit, but not by the encoding of the third bit.
18. An apparatus comprising: memory having associated instructions, that when executed, cause the apparatus to:
receive input data represented as a plurality of bits;
encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells;
control the plurality of multilevel memory cells in a manner to maintain a predetermined threshold Hamming distance between states of the plurality of multilevel memory cells, the states of the plurality of multilevel cells respectively corresponding to values of the plurality of bits; and
control the plurality of multilevel memory cells by detecting a predetermined value of the first plurality of bits; and level-shifting one or more of the plurality of multilevel memory cells, based at least in part on said detecting of the predetermined value.
19. An apparatus comprising memory having associated instructions that, when executed, cause the computer to: receive input data represented as a plurality of bits; and encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells, wherein the plurality of multilevel memory cells is M, each of the plurality of multilevel memory cells can be level-shifted a total of L times before being erased, the plurality of bits is B, a desired Hamming distance is H, and M, L, B, and H satisfy (M*L)>(B*H).
20. A system comprising: a memory, and a device capable of encoding a plurality of bits into a plurality of multilevel memory cells by
level-shifting a first subset of the plurality of multilevel memory cells to encode a first bit of the plurality of bits and a second subset of the plurality of multilevel memory cells to encode a second bit of the plurality of bits, wherein one of the plurality of multilevel memory cells is level-shifted by the encoding of the first bit and by the encoding of the second bit, and another of the plurality of multilevel memory cells is level shifted by the encoding of the first bit, but not by the encoding of the second bit.
21. The system of claim 20 , wherein the device is further capable of controlling the plurality of multilevel memory cells to maintain a Hamming distance between states of the plurality of multilevel memory cells.
22. The system of claim 20 , wherein the device is further capable of
level-shifting a third subset of the plurality of multilevel memory cells to encode a third bit of the plurality of bits, wherein yet another of the multilevel memory cells is level-shifted by the encoding of the second bit and by the encoding of the third bit, and still another of the multilevel memory cells is level-shifted by the encoding of the second bit, but not by the encoding of the third bit.
23. A system comprising: a host device; and a non-volatile memory device, coupled to the host device and configured to receive, from the host device, input data represented as a plurality of bits, and encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells, wherein the non-volatile memory device is further configured to control the plurality of multilevel memory cells in a manner to maintain a predetermined threshold Hamming distance between states of the plurality of multilevel memory cells, the states of the plurality of multilevel cells respectively corresponding to values of the plurality of bits, and wherein the non-volatile memory device is configured to control the plurality of multilevel memory cells by being configured to: detect a predetermined value of the first plurality of bits; and level-shift one or more of the plurality of multilevel memory cells, based at least in part on said detecting of the predetermined value.
24. A system comprising: a host device; and a non-volatile memory device, coupled to the host device and configured to receive, from the host device, input data represented as a plurality of bits, and encode the plurality of bits into a plurality of multilevel memory cells by level-shifting a subset of the plurality of multilevel memory cells to program a bit of the plurality of bits, wherein the subset includes two or more multilevel memory cells, and wherein the plurality of multilevel memory cells is M, each of the plurality of multilevel memory cells can be level-shifted a total of L times before being erased, the plurality of bits is B, a desired Hamming distance is H, and M, L, B, and H satisfy (M*L)>(B*H).
25. A method of encoding a plurality of bits in a plurality of multilevel memory cells comprising: level-shifting a plurality of multilevel memory cells at least as follows:
a first multilevel memory cell of the plurality to encode a first bit,
a second multilevel memory cell of the plurality to encode the first bit,
the second multilevel memory cell of the plurality to encode a second bit, and
a third multilevel memory cell of the plurality to encode the second bit.
26. The method of claim 25 , and further comprising: the level-shifting the plurality of the multilevel memory cells further comprising at least as follows:
the third multilevel memory cell of the plurality to encode a third bit, and
a fourth multilevel memory cell of the plurality to encode the third bit.