Secure memory device erase
View Patent ↗Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.
1. A method comprising:
storing data in locations of a memory device using two or more program states corresponding to threshold voltages, said program states being accessible from entities external to said memory device;
programming said locations to one or more intermediate states corresponding to voltages other than said threshold voltages, wherein said one or more intermediate states are defined internally to said memory device in response to receiving an erase command, wherein said one or more intermediate states are not readable from and not writable from an entity external to said memory device; and
erasing said locations programmed to said one or more intermediate states.
2. The method of claim 1 , further comprising:
performing a program-verify process for programming said locations in said one or more intermediate states.
3. The method of claim 2 , further comprising:
determining whether said erase command comprises a secure erase command or a normal erase command; and
modifying said program-verify process based at least in part on said determination.
4. The method of claim 1 , wherein said two or more program states are readable and writable from an entity external to said memory device.
5. The method of claim 1 , wherein said programming said locations in said one or more intermediate states comprises adding electrical charge to floating gates of one or more memory cells in said memory device.
6. A memory device comprising:
a plurality of memory cells;
an interface to receive an erase command from an entity external to said memory device, wherein said external entity defines threshold voltages of said memory cells as corresponding to program states; and
circuitry internal to said memory device, said circuitry to program said one or more memory cells to one or more intermediate states corresponding to voltages other than said threshold voltages and to subsequently erase said programmed one or more memory locations in response to receiving said erase command, wherein said one or more intermediate states are defined internally to said memory device, wherein said one or more intermediate states are not readable from and not writable from an entity external to said memory device.
7. The memory device of claim 6 , further comprising:
an internal memory management (IMM) portion to provide a program-verify process to program said memory locations to said state one or more intermediate states.
8. The memory device of claim 7 , wherein said IMM portion is capable of modifying said program-verify process based, at least in part, on whether said erase command comprises a secure erase command or a normal erase command.
9. The memory device of claim 6 , wherein said circuitry is further adapted to program said memory locations to two or more program states that are readable and/or writable from said entity external to said memory device.
10. The memory device of claim 6 , wherein said one or more intermediate states are associated with a particular amount of electrical charge on floating gates of memory cells located at least at one of said memory locations in said memory device.
11. The memory device of claim 10 , wherein said memory cells comprise NAND memory cells.
12. A system comprising:
a memory controller,
a memory device; and
an internal memory management (IMM) portion to:
store data in locations of said memory device using two or more program states corresponding to threshold voltages, said program states being accessible from entities external to said memory device; and
program said locations to one or more intermediate states corresponding to voltages other than said threshold voltages defined internally to said memory device in response to receiving an erase command from said memory controller, wherein said one or more intermediate states are not readable from and not writable from an entity external to said memory device;
erase said locations programmed to said one or more intermediate states; and
a processor to host one or more applications and to initiate commands to said memory controller to provide access to said memory device.
13. The system of claim 12 , wherein said entities external to said memory device comprise said memory controller.
14. The system of claim 12 , wherein said IMM portion is further adapted to perform a program-verify process for programming said stored data in said one or more intermediate states.
15. The system of claim 14 , wherein said IMM portion is further adapted to:
determine whether said erase command comprises a secure erase command or a normal erase command; and
modify said program-verify process based on said determination.
16. The system of claim 12 , wherein said two or more program states are readable and/or writable external to said memory device.
17. The system of claim 12 , wherein said memory device comprises a NAND memory device.