Shallow trench isolation for a memory
View Patent ↗In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.
1. A method comprising:
forming a first gate structure over a microelectronic substrate;
forming a spacer on said structure; and
using said spacer as a mask to etch shallow trench isolation trenches in said substrate extending in a first direction;
leaving an unetched portion of said substrate between said shallow trench isolation trenches and edges of said structure; and
forming a source and drain aligned in said first direction.
2. The method of claim 1 including forming a flash memory using said structure.
3. The method of claim 1 including forming a nitride layer over said structure.
4. The method of claim 3 wherein forming a spacer includes forming sidewall spacers.
5. The method of claim 4 including leaving an upstanding portion of said substrate between two parallel shallow trench isolation trenches.
6. The method of claim 5 including forming a two part floating gate with an upper part contacting and overhanging the first gate structure.
7. The method of claim 6 including filling said shallow trench isolation trenches with a filler before forming said upper part.
8. The method of claim 7 including forming trenches in said filler down to said structure and removing said nitride layer.
9. The method of claim 8 including forming said upper part by depositing doped polysilicon over the first gate structure formed of undoped polysilicon.
10. A method comprising:
forming a floating gate structure on a microelectronic substrate;
forming two shallow trench isolations outbound of said gate structure on said substrate;
defining a region of the substrate not covered by said gate structure between each shallow trench isolation and an adjacent edge of said gate structure; and
using a first portion of said gate structure as a mask to form said shallow trench isolations and, after forming said shallow trench isolations, forming a second portion of said gate structure overhanging said first portion.
11. The method of claim 10 including defining said region using a spacer.
12. The method of claim 11 including forming sidewall spacers to define said region.
13. A method comprising:
forming a first gate structure over a microelectronic substrate;
forming a spacer on said structure; and
using said spacer as a mask to etch shallow trench isolation trenches in said substrate, spaced from said first gate structure by said spacer, including forming a two part floating gate with an upper part contacting and overhanging the first gate structure.
14. The method of claim 13 including filling said shallow trench isolation trenches with a filler before forming said upper part.
15. The method of claim 14 including forming a nitride layer over said structure and forming trenches in said filler down to said structure said removing said nitride layer.
16. The method of claim 15 including forming said upper part by depositing doped polysilicon over first gate structure formed of undoped polysilicon.
17. A method comprising:
forming a floating gate structure on a microelectronic substrate;
forming two shallow trench isolations outbound of gate structure on said substrate; and
defining a region of the substrate not covered by said gate structure between each shallow trench isolation and an adjacent edge of said gate structure including using a first portion of said gate structure as a mask to form said shallow trench isolations and, after forming said shallow trench isolations, forming a second portion of said gate structure overhanging said fist portion.