Write performance of phase change memory using set-pulse shaping
View Patent ↗Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
1. A method comprising:
applying a bias signal pulse to a terminal of one or more word lines or bit lines of a plurality of phase change memory (PCM) cells comprising a phase change material to set said PCM cells in response to a write command;
crystallizing at least a portion of said phase change material by decreasing a voltage of said bias signal pulse at a first range of rates based, at least in part, on one or more physical attributes of a first population of said plurality of PCM cells; and
crystallizing at least another portion of said phase change material by decreasing a voltage of said bias signal pulse at a second range of rates different from said first range of rates based, at least in part, on one or more physical attributes of a second population of said plurality of PCM cells.
2. The method of claim 1 , further comprising:
crystallizing at least an additional portion of said phase change material by decreasing a voltage of said bias signal pulse at a third range of rates different from said first and second ranges of rates based, at least in part, on one or more physical attributes of a third population of said plurality of PCM cells.
3. The method of claim 1 , wherein said bias signal pulse comprises a single pulse of a voltage and/or current signal.
4. The method of claim 1 , wherein said bias signal pulse comprises a smooth concave-up set ramp.
5. The method of claim 1 , wherein said one or more physical attributes comprise memory cell electrical characteristics.
6. The method of claim 1 , wherein said phase-change material comprises germanium antimony telluride (GST).
7. A non-volatile memory device comprising:
an array of phase change memory (PCM) cells comprising a phase change material; and
a controller to:
apply a bias signal pulse to a terminal of one or more word lines or bit lines of said array of PCM cells to set said PCM cells in response to a write command;
crystallize at least a portion of said phase change material by decreasing a voltage of said bias signal pulse at a first range of rates based, at least in part, on one or more physical attributes of a first population of said array of PCM cells; and
crystallize at least another portion of said phase change material by decreasing a voltage of said bias signal pulse at a second range of rates different from said first range of rates based, at least in part, on one or more physical attributes of a second population of said array of PCM cells.
8. The non-volatile memory device of claim 7 , further comprising:
a ramp-generating circuit to provide said bias signal pulse at said first range of rates for a first duration and to provide said bias signal pulse at said second range of rates for a second duration.
9. The non-volatile memory device of claim 7 , wherein said controller is further adapted to crystallize at least an additional portion of said phase change material by decreasing a voltage of said bias signal pulse at a third range of rates different from said first and second ranges of rates based, at least in part, on one or more physical attributes of a third population of said plurality of PCM cells.
10. The non-volatile memory device of claim 9 , further comprising:
a ramp-generating circuit to provide said bias signal pulse at said first range of rates for a first duration, to provide said bias signal pulse at said second range of rates for a second duration, and to provide said bias signal pulse at said third range of rates for a third duration.
11. The non-volatile memory device of claim 7 , wherein said bias signal pulse comprises a smooth concave-up set ramp.
12. The non-volatile memory device of claim 7 , wherein said one or more physical attributes comprise memory cell electrical characteristics.
13. The non-volatile memory device of claim 7 , wherein said phase-change material comprises germanium antimony telluride (GST).
14. A system comprising:
a memory device comprising an array of phase change memory (PCM) cells comprising a phase change material, said memory device further comprising a memory controller to:
apply a bias signal pulse to a terminal of one or more word lines or bit lines of said array of PCM cells to set said PCM cells in response to a write command;
crystallize at least a portion of said phase change material by decreasing a voltage of said bias signal pulse at a first range of rates based, at least in part, on one or more physical attributes of a first population of said array of PCM cells; and
crystallize at least another portion of said phase change material by decreasing a voltage of said bias signal pulse at a second range of rates different from said first range of rates based, at least in part, on one or more physical attributes of a second population of said array of PCM cells; and
a processor to host one or more applications and to initiate said write command to said memory controller to provide access to said memory cells in said memory cell array.
15. The system of claim 14 , further comprising:
a ramp-generating circuit to provide said bias signal pulse at said first range of rates for a first duration and to provide said bias signal pulse at said second range of rates for a second duration.
16. The system of claim 14 , wherein said controller is further adapted to crystallize at least an additional portion of said phase change material by decreasing a voltage of said bias signal pulse at a third range of rates different from said first and second range of rates based, at least in part, on one or more physical attributes of a third population of said plurality of PCM cells.
17. The system of claim 16 , further comprising:
a ramp-generating circuit to provide said bias signal pulse at said first range of rates for a first duration, to provide said bias signal pulse at said second range of rates for a second duration, and to provide said bias signal pulse at said third range of rates for a third duration.
18. The system of claim 14 , wherein said bias signal pulse comprises a single substantially constant steady state portion of a voltage and/or current signal.
19. The system of claim 14 , wherein said one or more physical attributes comprise memory cell electrical characteristics.
20. The system of claim 14 , wherein said phase-change material comprises germanium antimony telluride (GST).