IP Library Granted Patent US 8,898,417
Granted Patent B1
US 8,898,417 · App. 12/582,643 · Granted Nov 25, 2014

Block-based storage device with a memory-mapped interface

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Quick Facts
Patent No.
US 8,898,417
App. No.
12/582,643
Granted
Nov 25, 2014
Kind
B1
Abstract

Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Claims (53)

1. An apparatus, comprising:

a storage array to store data;

a memory-mapped interface having memory-mapped memory space coupled to the storage array, the memory-mapped interface to receive direct access requests to directly access memory-mapped files via the memory-mapped memory space;

a block interface coupled to the storage array, the block interface to receive block requests from a storage driver to access the storage array;

memory-mapped setup logic configured to make regions of the storage array available in the memory-mapped memory space if the regions of the storage array are available, the memory-mapped setup logic configured to determine whether to evict a prior mapping from a vector table if the regions of the storage array are not available, and the memory-mapped setup logic configured to provide an error message if no eviction occurs;

processing logic configured to check whether address space having an address and size is available in the vector table, if no address space is available the processing unit returns an error message, if the address space is available the processing logic determines whether the direct access requests conflict with any block requests for the block interface; and

synchronization logic configured to resolve any conflicts between the direct access requests and any block requests for the block interface determined by the processing logic.

2. The apparatus of claim 1 , wherein the memory-mapped setup logic is configured to process a control signal received from the storage driver to make the regions of the storage array available in the memory-mapped memory space.

3. The apparatus of claim 2 , memory-mapped setup logic is further configured to update the vector table with mapping information.

4. The apparatus of claim 3 , further comprising:

memory-mapped data transfer logic is configured to intercept direct access requests to the memory-mapped memory space and redirect the direct access requests to an appropriate location in the storage array indicated by the vector table.

5. The apparatus of claim 4 , wherein the storage driver to send a request to the block interface if the request is a block request.

6. The apparatus of claim 5 , wherein a memory-mapped capable file system to directly access file allocation tables or other metadata that are stored in the storage array via the memory-mapped interface.

7. The apparatus of claim 1 , wherein the block interface is configured to access unmapped files from the storage array without accessing the memory-mapped memory space.

8. The apparatus of claim 1 , wherein the block interface is unauthorized to access the memory-mapped memory space.

9. A data processing device, comprising:

a processing unit having first and second processor cores;

system memory coupled to the processing unit, the system memory having an integrated circuit device comprising a storage array to store data;

a memory-mapped interface having memory-mapped memory space coupled to the storage array, the memory-mapped interface to receive direct access requests to access memory-mapped files via the memory-mapped memory space;

a block interface coupled to the storage array, the block interface to receive block requests to access the storage array;

memory-mapped setup logic configured to make regions of the storage array available in the memory-mapped memory space if the regions of the storage array are available, the memory-mapped setup logic configured to determine whether to evict a prior mapping from a vector table if the regions of the storage array are not available, and the memory-mapped setup logic configured to provide an error message if no eviction occurs;

processing logic configured to check whether address space having an address and size is available in the vector table, if no address space is available the processing unit returns an error message, if the address space is available the processing logic determines whether the direct access requests conflict with any block requests for the block interface; and

synchronization logic configured to resolve any conflicts between the direct access requests and any block requests for the block interface determined by the processing logic.

10. The data processing device of claim 9 , wherein the memory-mapped setup logic is configured to process a control signal received from the storage driver to make the regions of the storage array available in the memory-mapped memory space.

11. The data processing device of claim 10 , memory-mapped setup logic is further configured to update the vector table with mapping information.

12. The data processing device of claim 11 , further comprising:

memory-mapped data transfer logic is configured to intercept direct access requests to the memory-mapped memory space and redirect the direct access requests to an appropriate location in the storage array indicated by the vector table.

13. The data processing device of claim 9 , wherein the storage driver to send a request to the block interface if the request is a block request.

14. The data processing device of claim 13 , wherein the block request to request access to one or more sectors in a block interface command queue located in the block interface.

15. A method, comprising:

determining whether a control signal indicates a request is directed to a memory-mapped interface or a block-based interface, the memory-mapped interface having memory-mapped memory space coupled to a block-based storage device,

making regions of the block-based storage device available in the memory-mapped memory space if the regions of the storage array are available;

determining whether to evict a prior mapping from a vector table;

providing an error message if no eviction occurs;

processing the request to access the block-based storage device via the memory-mapped interface if the request is requesting access to the memory-mapped interface;

checking whether address space having an address and size is available in the vector table;

returning an error message if no address space is available;

determining whether the request conflicts with any block requests for the block interface if the address space is available;

resolving any conflicts between the request and any block requests for the block interface using interface synchronization logic associated with the block-based storage device.

16. The method of claim 15 , further comprising:

receiving a control signal that requests the address space in a memory-mapped window.

17. The method of claim 15 , further comprising:

processing the request to access the block-based storage device via a block interface if the request is a block request.

18. A non-transitory computer-readable storage medium storing instructions which, when executed by at least one processor, cause the at least one processor to perform operations comprising:

determining whether a control signal indicates a request is directed to a memory-mapped interface or a block-based interface, the memory-mapped interface having memory-mapped memory space coupled to a block-based storage device,

making regions of the block-based storage device available in the memory-mapped memory space if the regions of the storage array are available;

determining whether to evict a prior mapping from a vector table;

providing an error message if no eviction occurs;

processing the request to access the block-based storage device via the memory-mapped interface if the request is requesting access to the memory-mapped interface;

checking whether address space having an address and size is available in the vector table;

returning an error message if no address space is available;

determining whether the request conflicts with any block requests for the block interface if the address space is available;

resolving any conflicts between the request and any block requests for the block interface using interface synchronization logic associated with the block-based storage device.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2010
From: POST, SAM; HULBERT, JARED; BOWERS, STEPHEN; LEINWANDER, MARK
To: NUMONYX B.V.
Reel/Frame 024775/0267 →