Via formation for cross-point memory
View Patent ↗Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.
1. A method for forming one or more vias as part of a cross-point array memory device, comprising:
performing a first lithographic patterning operation to form a first electrode layer and a memory material layer on a substrate and to form one or more via placeholders comprising the memory material layer; and
forming said one or more vias defined at least in part by said one or more via placeholders.
2. The method of claim 1 , further comprising depositing a selector material layer over the first electrode layer and the memory material layer, wherein said one or more via placeholders further comprise elements patterned in the selector material layer.
3. The method of claim 2 , further comprising performing a second lithographic patterning operation to form a second electrode layer electrically coupled to said one or more vias.
4. The method of claim 3 , wherein said performing the first lithographic patterning operation comprises forming a plurality of lines oriented in a first direction comprising first electrode layer material, memory layer material, and selector layer material.
5. The method of claim 3 , wherein said performing the second lithographic patterning operation to form the second electrode layer comprises forming a plurality of electrically conductive lines for the second electrode layer oriented in a second direction, wherein said second direction is substantially orthogonal to said first direction.
6. The method of claim 3 , wherein said forming one or more vias defined at least in part by said one or more via placeholders comprises forming said one or more vias by patterning memory layer material and selector layer material in an area outside that designated for a memory array.
7. The method of claim 6 , wherein said forming said one or more vias comprises encapsulating an area surrounding said one or more via placeholders with a dielectric material, etching away memory layer material and selector layer material from the via placeholders, and depositing an electrically conductive material in holes formed by said etching.