Reduced signal interface memory device, system, and method
View Patent ↗A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one.
1. A wireless communications device comprising:
a transceiver to receive over-the-air signals;
a processor coupled to the transceiver, the processor having a first serial port with a bidirectional data pad; and
a serial memory device having a second serial port with a serial data out pad and with a serial data in pad coupled to the bidirectional data pad of the processor; a serial shift register coupled to receive input data from the serial data in pad and to provide output data to the serial data out pad; a switching device to couple the serial data out pad to the serial data in pad in response to a control signal; and a control unit to modify the control signal to effect bidirectional communications on the serial data in pad in response to a command received on the serial data in pad.
2. The wireless communications device of claim 1 further comprising a package housing the serial memory device, the package having a first conductor bonded to the serial data in pad, and a second conductor bonded to the serial data out pad.
3. The wireless communications device of claim 1 further comprising a package housing the serial memory device, the package having a first conductor bonded to the serial data in pad, and wherein the data out pad is left unbonded.
4. The wireless communications device of claim 1 wherein the serial memory device further comprises nonvolatile memory coupled to the serial shift register.
5. The wireless communications device of claim 4 wherein the nonvolatile memory comprises FLASH memory.
6. The wireless communications device of claim 4 wherein the nonvolatile memory comprises phase change memory.
7. A wireless communications device comprising:
a transceiver to receive over-the-air signals;
a processor coupled to the transceiver, the processor having a first serial port with a bidirectional data pad; and
a nonvolatile memory device having a second serial port with a serial data out pad and with a serial data in pad coupled to the bidirectional data pad of the processor, the serial data in pad of the nonvolatile memory being programmable to operate bidirectionally to reduce an interface signal count by one.
8. The wireless communications device of claim 7 wherein the processor includes a data store having an instruction that when transmitted to the nonvolatile memory device causes the serial data in pad to operate bidirectionally.
9. The wireless communications device of claim 7 wherein the nonvolatile memory device includes FLASH memory.
10. The wireless communications device of claim 7 wherein the nonvolatile memory device includes phase change memory.
11. A method comprising:
receiving an instruction on a serial data input pad of a memory device, the instruction specifying whether to use the serial data input pad and a serial data output pad for full duplex communications or to use the serial data input pad for bidirectional communications; and
in response to the instruction, performing memory operations using bidirectional serial communications on the serial data input pad.
12. The method of claim 11 wherein performing memory operations comprises:
receiving a read instruction and an address on the serial data input pad;
accessing memory data at the address; and
sending the memory data on the serial data input pad.
13. The method of claim 12 wherein accessing the memory comprises accessing a nonvolatile memory.
14. The method of claim 13 wherein accessing a nonvolatile memory comprises accessing a FLASH memory.
15. The method of claim 13 wherein accessing a nonvolatile memory comprises accessing a phase change memory.