Integration of resistors and capacitors in charge trap memory device fabrication
View Patent ↗A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.
1. A method of fabricating a semiconductor device structure, the method comprising:
forming a dielectric layer of a charge trapping dielectric stack for a non-volatile memory cell, the dielectric layer being disposed over a first conductor peripheral to the memory cell;
patterning the dielectric layer to expose a portion of the first conductor;
forming a conductive material over the dielectric layer and in contact with the exposed portion of the first conductor; and
patterning the conductive material to form circuitry including the first conductor and to form a portion of the memory cell, the patterning of the conductive material further comprising removing a portion of the conductive material to form a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor.
2. The method of claim 1 , wherein the first conductor is a patterned layer disposed over a semiconductor substrate or is a doped region of the semiconductor substrate.
3. The method of claim 1 , wherein the dielectric layer is a charge trapping layer of the charge trapping dielectric stack.
4. The method of claim 1 , wherein patterning the dielectric layer further comprises: forming, in the dielectric layer, a first contact opening and a second contact opening spaced apart from one another to expose two distinct regions of the first conductor.
5. The method of 1 , wherein patterning the conductive material further comprises retaining a second portion of the conductive material contacting the first conductor to form conductive heads of a resistor.
6. The method of claim 1 , wherein the dielectric layer is a silicon nitride or a high-k dielectric having a dielectric constant greater than a silicon nitride and wherein the first conductor is a patterned poly-silicon or metal feature.
7. The method of claim 1 , wherein the memory cell is a NAND memory cell.
8. A semiconductor device structure, comprising:
a memory cell region of a substrate, the memory cell region including a non-volatile charge trapping dielectric stack;
a peripheral region of the substrate, the peripheral region including a dielectric layer of the non-volatile charge trapping dielectric stack disposed over a first conductor;
circuitry formed from a conductive material including the first conductor to form a portion of the semiconductor device structure as a resistor element; and
a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor.
9. The semiconductor device structure of claim 8 , wherein the dielectric layer is disposed over only a portion of the first conductor.
10. The semiconductor device structure of claim 8 , wherein the first conductor is a patterned layer disposed over a semiconductor substrate or is a doped region of the semiconductor substrate.
11. The semiconductor device structure of claim 8 , wherein the dielectric layer is a charge trapping layer of the charge trapping dielectric stack.
12. The semiconductor device structure of claim 8 , further comprising:
a first conductive contact and a second conductive contact disposed over the dielectric layer, wherein each of the first conductive contact and the second conductive contact is electrically coupled with a distinct portion of the first conductor.
13. The semiconductor device structure of claim 12 , wherein a portion of the first conductor forms a resistor.
14. The semiconductor device structure of claim 8 , wherein the dielectric layer is a silicon nitride or a high-k dielectric having a dielectric constant greater than the silicon nitride and wherein the first conductor is a patterned poly-silicon or a metal feature.
15. A method of fabricating a semiconductor device structure, the method comprising:
patterning a conductive layer into a transistor gate and at least one of a capacitor plate or a resistor in a peripheral region of the semiconductor device;
depositing a dielectric layer as part of a non-volatile charge trapping dielectric stack of a memory cell in an array region of the semiconductor device; and
patterning a portion of the dielectric layer disposed over the peripheral region to expose the entire transistor gate, but expose only a portion of the capacitor plate or expose only a portion of the resistor.
16. The method of claim 15 , further comprising forming a conductive layer on the non-volatile charge trapping dielectric stack, on the transistor gate and in contact with the portion of the capacitor plate or resistor.