Phase-change memory temperature sensitive detector
View Patent ↗A Phase-Change Memory (PCM) having a temperature detector with a dedicated PCM bit programmed to an amorphous state and a circuit to determine that the dedicated PCM bit is no longer in the amorphous state. A temperature exposure signal is asserted to indicate that a high temperature has altered PCM device programming integrity.
1. A Phase-Change Memory (PCM) device, comprising:
at least one memory array having a plurality of PCM memory cells; and
one or more dedicated PCM temperature detector cells to make a determination whether the PCM device has been subjected to a predetermined temperature sufficient to alter a programmed value of a high-resistance amorphous state of the plurality of PCM memory cells to a lower resistance state, the alteration being indicative of unreliable data storage in the PCM memory cells.
2. The PCM device of claim 1 , wherein the one or more dedicated PCM temperature detector cells is programmed to a high-resistance amorphous state by a manufacturer following semiconductor processing.
3. The PCM device of claim 1 , wherein the one or more dedicated PCM temperature detector cells is programmed to a high-resistance amorphous state when the PCM device is powered on.
4. The PCM device of claim 1 , further comprising a sense/write circuit, wherein the one or more dedicated PCM temperature detector cells and the sense/write circuit form a temperature detector to determine an existence of a past history indicative of the PCM device having been subjected to at least the predetermined temperature.
5. The PCM device of claim 4 , wherein the temperature detector is configured to detect PCM memory cell resistance changes that are deterministic of temperature effects on the PCM device that result in memory cell data loss in the PCM device.
6. The PCM device of claim 4 , wherein the sense/write circuit asserts a temperature exposure signal when the temperature detector determines that the PCM device has been subjected to at least the predetermined temperature.
7. The PCM device of claim 1 , wherein the one or more dedicated PCM temperature detector cells have been manufactured using a same processes as the plurality of PCM memory cells of the PCM device.
8. A Phase-Change Memory (PCM) device, comprising:
at least one PCM array of memory cells;
a dedicated PCM bit; and
a compare circuit to receive a current from the dedicated PCM bit to compare against a reference current to assert a temperature exposure signal based on a determination that at least one of the memory cells was subjected to a temperature sufficient to alter a programmed value of a high-resistance amorphous state of the at least one of the memory cells to a lower resistance state sufficient to cause unreliable data storage in the at least one of the memory cells.
9. The PCM device of claim 8 , wherein the dedicated PCM bit and the compare circuit form a temperature detector circuit.
10. The PCM device of claim 9 configured to receive a memory command to program the dedicated PCM bit to a high resistance state that resets the temperature detector circuit for future use.
11. The PCM device of claim 8 , wherein the assertion of the temperature exposure signal indicates that the PCM has been subjected to a high temperature that has altered PCM device programmed integrity of the high-resistance amorphous state of the PCM device.
12. The PCM device of claim 8 , wherein the temperature exposure signal not being asserted indicates that the PCM has not undergone a high temperature that has altered an amorphous state of the PCM device.
13. A Phase-Change Memory (PCM) device, comprising:
a PCM array; and
a PCM temperature detector having a dedicated PCM bit programmed to an amorphous state and a circuit to determine whether the dedicated PCM bit is no longer in the amorphous state based on exposure to a temperature sufficient to alter a programmed value of a high-resistance amorphous state of the at least one of a plurality of memory cells in the PCM array to a lower resistance state sufficient to cause unreliable data storage in the PCM array and to assert a temperature exposure signal.
14. The PCM device of claim 13 , wherein the temperature exposure signal indicates that the PCM device has been subjected to the temperature that has altered integrity of the high-resistance amorphous state of the PCM array.
15. The PCM device of claim 13 , wherein the PCM device and the circuit form a temperature detector that tests amorphous state stability when triggered by the PCM device.
16. The PCM device of claim 15 , wherein the trigger is a power-on sequence of the PCM device.
17. The PCM device of claim 13 , further comprising multiple dedicated PCM cells in the PCM temperature detector to detect a temperature at least equal to the temperature that alters the programmed value of a high-resistance amorphous state of the PCM device.
18. The PCM device of claim 17 , wherein the multiple dedicated PCM cells have been manufactured using a same process as PCM cells in memory arrays of the PCM device.
19. The PCM device of claim 13 , the device being configured to initiate a data refresh operation to recover data when, during operation of the PCM device, data integrity is determined to be marginal based on a determination of the alteration of the programmed value of a high-resistance amorphous state of the PCM device.