Cache coherence protocol for persistent memories
View Patent ↗A memory device having a memory controller, a main memory with at least a portion comprising persistent memory, and at least two processing entities, wherein the memory controller enables the processing entities to access the main memory according to a cache coherence protocol. The cache coherency protocol can signal when the main memory is being updated and when the update has finished. The processing entities can be configured to wait for the main memory to be updated or can access previously stored memory.
1. A memory device comprising:
a memory controller having at least a first interface to a main memory and at least a second interface to two or more processing entities, wherein said memory controller is configured to enable said processing entities to access said main memory according to a cache coherency protocol, the cache coherency protocol comprising an in-process state and a committed state;
wherein the in-process state indicates that information in the main memory is being updated, and the memory controller is configured to:
select between and perform actions of:
a). waiting to load the information updated during the in-process state from the main memory to a cache until the committed state indicates that a memory update is complete and the cache may reload information from the main memory, or
b). ignoring an update causing the in-process state and loading a previous cache content of the information;
wherein at least a portion of said main memory comprises persistent memory; and
wherein said memory controller is configured to enable a memory hierarchy including one or more levels of cache memory shared among said two or more processing entities, wherein at least a portion of said one or more levels of cache memory comprise persistent memory.
2. The memory device of claim 1 , wherein said memory controller is further configured to enable a memory descriptor to identify said at least a portion of said main memory comprising persistent memory.
3. The memory device of claim 1 , wherein said persistent memory comprises phase change memory (PCM).
4. The memory device of claim 1 , wherein said persistent memory comprises a memory having asymmetrical read/write speeds.
5. The memory device of claim 1 , wherein said two or more processing entities comprise a plurality of central processing units (CPUs).
6. The memory device of claim 1 , wherein said main memory is entirely persistent memory.
7. The memory device of claim 1 , wherein said processing entities access said persistent memory according to said cache coherency protocol.
8. A method comprising:
providing a memory device comprising a memory controller having at least a first interface to a main memory and at least a second interface to two or more processing entities; and
managing a cache coherency protocol comprising an in-process state and a committed state with the memory controller to allow the two or more processing entities to share the main memory-according to the cache coherency protocol;
wherein the in-process state indicates that information in the main memory is being updated, and the memory controller is configured to:
select between and perform actions of:
a). waiting to load the information updated during the in-process state from the main memory to a cache until the committed state indicates that a memory update is complete and the cache may reload information from the main memory, or
b). ignoring an update causing the in-process state and loading a previous cache content of the information;
wherein at least a portion of said main memory comprises persistent memory; and
wherein said memory controller is configured to enable a memory hierarchy including one or more levels of cache memory shared among said two or more processing entities, wherein at least a portion of said one or more levels of cache memory comprise persistent memory.
9. The method of claim 8 , wherein said persistent memory comprises phase change memory (PCM).
10. The method of claim 8 , wherein said persistent memory comprises a memory having asymmetrical read/write speeds.
11. The method of claim 8 , wherein said cache coherency protocol is based, at least in part, on one or more latency properties of said persistent memory.
12. The method of claim 8 , wherein said plurality of processing entities comprise one or more central processing units (CPUs).
13. A system comprising:
a plurality of processing entities; and
a memory device comprising:
a memory controller having at least a first interface to a main memory and at least a second interface to said plurality of processing entities, wherein said memory controller is configured to enable said plurality of processing entities to access said main memory according to a cache coherency protocol comprising an in-process state and a committed state;
wherein the in-process state indicates that information in the main memory is being updated, and the memory controller is configured to:
select between and perform actions of:
a). waiting to load the information updated during the in-process state from the main memory to a cache until the committed state indicates that a memory update is complete and the cache may reload information from the main memory, or
b). ignoring an update causing the in-process state and loading a previous cache content of the information;
wherein at least a portion of said main memory comprises persistent memory;
and wherein said memory controller is configured to enable a memory hierarchy including one or more levels of cache memory shared among said two or more processing entities, wherein at least a portion of said one or more levels of cache memory comprise persistent memory.
14. The system of claim 13 , wherein said memory controller is further configured to signal to at least one of said plurality of processing entities to wait to access said main memory during said update process.
15. The system of claim 13 , wherein said processing entity is configured to wait to access said main memory during said update process.