IP Library Granted Patent US 8,623,697
Granted Patent B2
US 8,623,697 · App. 13/132,311 · Granted Jan 7, 2014

Avoiding degradation of chalcogenide material during definition of multilayer stack structure

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Quick Facts
Patent No.
US 8,623,697
App. No.
13/132,311
Granted
Jan 7, 2014
Kind
B2
Abstract

A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer ( 206 ), a metal cap layer ( 208 ), and a dielectric hard mask layer ( 210 ), depositing and patterning a photo resist layer ( 212 ) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric ( 214 ) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers ( 216 ) for the multilayer stack.

Claims (68)

1. A method comprising:

forming a stack comprising

forming a metal heater layer,

forming a chalcogenide over the metal heater layer such that a lowermost portion of the chalcogenide is only partially in contact with the metal heater, and

forming a first dielectric on top of the chalcogenide;

defining the first dielectric using a photo resist as a mask, defining the first dielectric being followed by removing the photo resist prior to defining the chalcogenide;

defining the chalcogenide using the defined first dielectric as a mask; and

sealing sidewalls of the chalcogenide with a second dielectric.

2. The method of claim 1 , wherein the stack further comprises forming a metal cap over the chalcogenide, wherein defining the first dielectric further comprises defining the metal cap.

3. The method of claim 2 , wherein defining the metal cap uses Cl/Ar dry etch chemistry.

4. The method of claim 2 , wherein defining the metal cap partially removes the metal cap.

5. The method of claim 1 , wherein the photo resist is removed by O 2 /N 2 /H 2 based plasma dry removal process.

6. The method of claim 1 , wherein the chalcogenide is defined by CF 4 based dry etch chemistry.

7. The method of claim 1 , wherein sealing sidewalls of the chalcogenide with a second dielectric further comprises forming the second dielectric over the stack and anisotropically etching the second dielectric to form sidewall spacers for the chalcogenide.

8. The method of claim 7 , wherein etching the second dielectric further comprises:

forming a surrounding dielectric material on the sides of the metal heater layer;

etching the metal heater layer beneath the chalcogenide; and

etching the surrounding dielectric material formed on the sides of the metal heater layer.

9. The method of claim 8 , wherein etching the second dielectric uses SF 6 based dry etch chemistry.

10. The method of claim 1 , further comprises forming an enclosure dielectric over the stack after sealing the sidewalls of the chalcogenide.

11. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a metal heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, the metal heater being coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer with CF 4 based dry etch chemistry using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack.

12. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a metal heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, the metal heater being coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer, the photo resist layer being removed by O 2 /N 2 /H 2 based plasma dry removal process;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack.

13. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a metal heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, the metal heater being coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask, the chalcogenide layer being etched by CF 4 based dry etch chemistry;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack.

14. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a metal heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, the metal heater being coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack, the spacer dielectric being anisotropically etched by SF 6 based dry etch chemistry.

15. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a metal heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, forming the multilayer stack further comprising forming a surrounding first dielectric material on the sides of the metal heater and forming a second dielectric beneath the metal heater, the metal heater being coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack.

16. A method of forming a storage element structure, the method comprising:

forming a portion of a multilayer stack comprising a refractory ternary metal nitride heater and a dielectric hard mask layer with a chalcogenide layer disposed therebetween, the refractory ternary metal nitride heater comprising TiSiN, about 80 nm thick, coupled to a portion of a lowermost section of the chalcogenide layer;

depositing and patterning a photo resist layer on top of the portion of the multilayer stack;

etching the dielectric hard mask layer using the photo resist layer as an etch mask;

after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide layer;

etching the chalcogenide layer using the dielectric hard mask layer as an etch mask;

forming a spacer dielectric over at least a portion of the multilayer stack; and

anisotropically etching the spacer dielectric to form sidewall spacers for the at least the portion of the multilayer stack.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2013
From: MAGISTRETTI, MICHELE; PETRUZZA, PIETRO; SCIARRILLO, SAMUELE; CASELLATO, CRISTINA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031397/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →