Dual mode clock and data scheme for memory programming
View Patent ↗A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in the data transfer rate.
1. A Phase-Change Memory (PCM) device comprising a factory interface to receive factory program data on a data bus switching with a dual edge clock, the factory interface including transition detector circuit to generate a transition detector generated internal clock to provide a delayed edge to latch the factory program data for storage in the PCM device, wherein the factory interface is located in the PCM device.
2. The PCM device of claim 1 , wherein the transition detector circuit includes a two-input semiconductor device to receive the dual edge clock and a delayed version of the dual edge clock to generate a pulsed signal.
3. The PCM device of claim 2 , wherein the transition detector circuit detects a transition on the dual edge clock and generates the pulsed signal to latch the program data.
4. The PCM device of claim 1 , further including a program buffer coupled to the factory interface to receive latched program data to prepare for storage in PCM arrays.
5. A Phase-Change Memory (PCM) device, comprising:
a system memory interface to operate in a system mode selected as a default operating mode to receive data and commands from a data bus; and
a factory programming interface to operate in a factory programming mode to receive factory program data on the data bus and a dual edge clock that is used to generate an internal clock to provide a delayed edge to latch the factory program data, the factory programming interface including a circuit, wherein the factory programming interface is located in the PCM device.
6. The PCM device of claim 5 , wherein the factory program data received from an external source switches with transitions of the dual edge clock.
7. The PCM device of claim 5 , wherein a command received through the data bus instructs the PCM device to switch to the factory programming mode.
8. The PCM device of claim 5 , wherein another command received on the data bus instructs the PCM device to revert back to the system mode.
9. The PCM device of claim 5 , wherein an input pin directs the PCM device to operate in the system mode or the factory programming mode.
10. A Phase-Change Memory (PCM), comprising:
a PCM array;
a system memory interface operating in a system mode for executing system applications; and
a factory programming interface operating in a factory programming mode to receive program data on a data bus to overcome heat related storage failures associated with the PCM device, the factory programming interface including a circuit, wherein the factory programming interface is located in the PCM, wherein the factory programming interface receives factory program data switching with transitions of a dual edge clock, and wherein the circuit of the factory programming interface includes a transition detector circuit to generate an internal clock to provide a delayed edge to latch the factory program data for storage in the PCM.
11. The PCM of claim 10 , wherein the PCM redefines one or more control pins as data pins in a factory programming mode to increase a width of the data bus and increase a programming data rate.
12. The PCM of claim 10 , wherein the factory programming interface uses a dual-edge clock scheme to provide a doubling in the data transfer rate.
13. A Phase-Change Memory (PCM), comprising:
a PCM array;
a system memory interface operating in a system mode for executing system applications; and
a factory programming interface operating in a factory programming mode to receive program data on a data bus to overcome heat related storage failures associated with the PCM device, the factor programming interface including a circuit, wherein the factor programming interface is located in the PCM, wherein the circuit of the factory programming interface includes a transition detector circuit to receive the dual edge clock and a delayed version of the dual edge clock to generate a pulsed signal, and wherein the transition detector circuit detects a transition on the dual edge clock to generate the pulsed signal to latch the program data.
14. A nonvolatile memory device, comprising:
a system memory interface; and
a factory programming interface to receive factory program data and a dual edge clock, wherein the factory interface includes a transition detector circuit to receive the dual edge clock and generate a delayed version of the dual edge clock to provide a delayed edge to latch the factory program data for storage in the nonvolatile memory device, wherein the factory programming interface is located in the nonvolatile memory device.
15. The nonvolatile memory device of claim 14 , wherein the transition detector circuit includes an EXCLUSIVE-OR device to receive the dual edge clock and the delayed version of the dual edge clock to generate a pulsed signal to latch the factory program data.
16. The nonvolatile memory device of claim 14 , wherein the factory program data is stored in a Phase-Change Memory (PCM) device.