Reading threshold switching memory cells
View Patent ↗Using the voltage across a threshold switching cell to sense the state of the cell, rather than sensing current through the cell, may result in a faster read. In some embodiments, current consumption during reading of conductive states may be reduced by using a capacitor coupled across the cell.
1. A method comprising:
reading the state of a phase change threshold switching memory cell using a capacitor coupled in parallel with the cell; and
charging said capacitor to a voltage intermediate between two cell states to be distinguished upon reading the cell.
2. The method of claim 1 including determining the charge on the capacitor after coupling said cell across said capacitor.
3. The method of claim 2 including coupling a node of said capacitor to a voltage comparator and comparing a voltage on the node to a reference voltage.
4. The method of claim 3 including making said comparison after a time period has elapsed since coupling said capacitor to said cell.
5. The method of claim 1 including distinguishing between set and reset phase change memory states.
6. The method of claim 1 including distinguishing between levels of a multilevel cell.
7. The method of claim 1 including using parasitic capacitance as said capacitor.
8. A threshold switching memory comprising:
a phase change memory cell;
a capacitor selectively connectable across said cell;
a comparator to compare a voltage across said capacitor to a reference voltage to determine the state of said cell; and
a charging circuit to charge said capacitor to a level intermediate between two cell states to be distinguished upon reading the cell.
9. The memory of claim 8 , said comparator to compare a voltage on said capacitor to a reference voltage after coupling said cell across said capacitor.
10. The memory of claim 9 , said comparator to allow a time period to elapse after connecting said capacitor across said cell before comparing said voltage across said capacitor to said reference voltage.
11. The memory of claim 8 including a comparator to compare a reference voltage intermediate between the states to be distinguished upon reading the cell to a voltage on said capacitor.
12. The memory of claim 8 , said control to distinguish between levels of a multilevel cell.
13. The memory of claim 8 , said control to distinguish between set and reset phase change memory states.
14. The memory of claim 8 wherein said capacitor is parasitic capacitance from the memory itself.
15. The memory of claim 8 , said control to latch the value of the comparison between the voltage on the capacitor and the reference voltage.
16. A memory comprising:
a phase change memory cell;
a switch;
a controller to control said switch;
a capacitor selectively connectable by said switch across said memory cell; and
a charging circuit to charge said capacitor to a level intermediate between two cell states to be distinguished upon reading a cell.
17. The memory of claim 16 including a comparator to compare a voltage across said capacitor to a reference voltage.
18. The memory of claim 16 wherein said capacitor is parasitic capacitance from the memory itself.
19. The memory of claim 8 including a control to control the state of a first switch to couple said capacitor to said cell and a second switch to couple a voltage source to said capacitor.