BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE

1 . A method comprising:

determining a bit error rate and/or number of bit errors associated with signals representative of information read from a particular portion of a memory;

comparing said bit error rate and/or said number of bit errors to an error threshold; and

determining whether to retire said particular portion of said memory based at least in part on said comparing.

2 . The method of claim 1 , wherein retiring said particular portion of said memory comprises:

relocating said information represented by signals from said particular portion of said memory to another portion of said memory.

3 . The method of claim 2 , wherein said other portion of said memory comprises a spare memory region.

4 . The method of claim 1 , wherein said memory comprises a phase-change memory device.

5 . The method of claim 2 , further comprising:

remapping an address of said particular portion of said memory to said other portion of said memory.

6 . The method of claim 1 , wherein said bit error rate and/or said number of bit errors is responsive, at least in part, to a physical degradation of said memory.

7 . A device comprising:

an addressable memory;

an error counter to determine a bit error rate and/or the number of bit errors associated with signals representative of information read from a particular portion of said addressable memory;

a compare engine to compare said bit error rate and/or said number of bit errors to an error threshold; and

a controller to determine whether to retire said particular portion of said addressable memory based at least in part on said comparing.

8 . The device of claim 7 , wherein said controller is further adapted to relocate said information represented by signals from said particular portion of addressable memory to another portion of said addressable memory.

9 . The device of claim 8 , wherein said other portion of said addressable memory comprises a spare memory region.

10 . The device of claim 7 , wherein said addressable memory comprises a phase-change memory device.

11 . The device of claim 8 , wherein said controller is further adapted to remap an address of said particular portion of said addressable memory to said other portion of said addressable memory.

12 . The device of claim 7 , wherein said bit error rate and/or said number of bit errors is responsive, at least in part, to a physical degradation of said memory.

13 . An apparatus comprising:

means for determining a bit error rate and/or the number of bit errors associated with signals representative of information read from a particular portion of a memory;

means for comparing said bit error rate and/or said number of bit errors to an error threshold; and

means for determining whether to retire said particular portion of said memory based at least in part on said comparing.

14 . The apparatus of claim 13 , wherein retiring said particular portion of memory comprises:

means for relocating said information represented by signals from said particular portion of memory to another portion of said memory.

15 . The apparatus of claim 14 , further comprising:

means for remapping an address of said particular portion of said memory to said other portion of said memory.

16 . The apparatus of claim 13 , wherein said bit error rate and/or said number of bit errors is responsive, at least in part, to a physical degradation of said memory.

17 . An article comprising:

a storage medium comprising machine-readable instructions stored thereon which, if executed by a special purpose computing device, are adapted to enable said special purpose computing device to:

determine a bit error rate and/or number of bit errors associated with signals representative of information read from a particular portion of a memory;

compare said bit error rate and/or said number of bit errors to an error threshold; and

determine whether to retire said particular portion of said memory based at least in part on said comparing.

18 . The article of claim 17 , wherein said instructions, if executed by said special purpose computing device, are further adapted to enable said special purpose computing device to:

retire said particular portion of memory by relocating said information from said particular portion of said memory to another portion of said memory.

19 . The article of claim 17 , wherein said memory comprises a phase-change memory device.

20 . The article of claim 18 , wherein said instructions, if executed by said special purpose computing device, are further adapted to enable said special purpose computing device to:

remap an address of said particular portion of said memory to said other portion of said memory.