Hierarchical memory architecture using a concentrator device
View Patent ↗A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices.
1. A concentrator device having a frontside port to couple to a processor and provide hierarchical storage to memory devices coupled to a backside port substantially opposite to the frontside port, wherein the concentrator device is positioned between the frontside port and the backside port to separate the memory devices attached to the backside port from the frontside port, and data received from the backside port is cached in a Phase-Change Memory (PCM), and wherein the concentrator device includes an Error-Correcting Code (ECC) engine to provide error detection and correction.
2. The concentrator device of claim 1 , wherein the concentrator device provides an interface to the memory devices having different formats.
3. The concentrator device of claim 1 , further including;
a page buffer coupled to the frontside port to receive data words to hold for programming into the PCM; and
a command queue for issuing memory commands.
4. The concentrator device of claim 1 , wherein the PCM includes at least a first memory array and a second memory array to split code and data spaces.
5. The concentrator device of claim 1 , further including a NAND host state machine to control operations of the concentrator device and accommodate a NAND memory coupled to the backside port.
6. The concentrator device of claim 1 , wherein the backside port is configured to communicate over a half-duplex bidirectional bus.
7. The concentrator device of claim 1 , wherein the backside port is configured to communicate over a full-duplex bidirectional bus.
8. The concentrator device of claim 1 , further including a second backside port.
9. The concentrator device of claim 1 , further including a Random Access Memory (RAM).
10. The concentrator device of claim 9 , further including a flush pin to initiate dumping contents of the RAM to the PCM.
11. A concentrator device to separate external memory devices from a processor, comprising:
a frontside bus port to receive data from the processor, and a backside port substantially opposite to the frontside bus port and coupled to the external memory devices, wherein the concentrator device is positioned between the frontside bus port and the backside port to separate the external memory devices attached to the backside port from the frontside bus port;
a Phase-Change Memory (PCM) memory array;
a page buffer to store the data received from the processor for programming into the PCM memory array;
a command queue for issuing memory commands; and
an Error-Correcting Code (ECC) engine to provide error detection and correction.
12. The concentrator device of claim 11 , further including a Random Access Memory (RAM) and a flush pin to dump contents of the RAM to the PCM memory array.
13. The concentrator device of claim 11 , further including a Random Access Memory (RAM), where the command queue issues a flush command to dump contents of the RAM to the PCM memory array.
14. The concentrator device of claim 11 , wherein the Error-Correcting Code engine is configured to provide error detection and correction schemes appropriate to the external memory devices.
15. The concentrator device of claim 11 , further including a Content Addressable Memory (CAM) to store addresses of defective memory locations in the PCM memory array.
16. The concentrator device of claim 15 , wherein the CAM stores addresses of defective memory locations for memories attached to the backside port.
17. A concentrator device to couple external memory devices to a processor, comprising:
a frontside port coupled to the processor, and a backside port substantially opposite to the frontside port and coupled to the external memory devices, wherein the concentrator device is positioned between the frontside port and the backside port to separate the external memory devices attached to the backside port from the frontside port;
a page buffer to hold data received from the processor;
a Phase-Change Memory (PCM) memory array to store the data transferred from the page buffer; and
a configurable Error-Correcting Code (ECC) engine to provide error detection and correction for the data written to the PCM memory array, where the page buffer, PCM and ECC engine in the concentrator device accommodate temporary storage for data transfers between the processor and the external memory devices.
18. The concentrator device of claim 17 , further including a Content Addressable Memory (CAM) to store addresses of memory locations in the PCM memory array or addresses of defective memory locations in the external memory devices defective.
19. The concentrator device of claim 17 , further including a NAND host state machine to control operations of the concentrator device in accommodating a NAND memory as one of the external memory devices.
20. The concentrator device of claim 17 , further including General Purpose Input/Output (GPIO) pins.