Phase change memory device with reduced programming disturbance
View Patent ↗A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.
1. A Phase Change Memory device comprising:
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element directly coupled to the second bit line to control a voltage of the second bit line during a programming operation of the memory cell.
2. The Phase Change Memory device of claim 1 further comprising:
a second memory cell coupled to the first word line and to the second bit line, wherein the voltage controlling element is further to inhibit programming of the second memory cell.
3. The Phase Change Memory device of claim 1 wherein the voltage controlling element is coupled to a voltage control word line.
4. The Phase Change Memory device of claim 1 wherein the voltage controlling element comprises a voltage controlling transistor.
5. The Phase Change Memory device of claim 4 wherein the voltage controlling transistor is coupled between the second bit line and a voltage generator.
6. The Phase Change Memory device of claim 5 wherein a voltage control word line is coupled to a gate terminal of the voltage controlling transistor.
7. A Phase Change Memory device comprising:
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element coupled to the second bit line to control a voltage of the second bit line during a programming operation of the memory cell, wherein the voltage controlling element comprises a voltage controlling diode and the voltage controlling diode is coupled between the second bit line and the voltage control word line.
8. A Phase Change Memory device comprising:
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element coupled to the second bit line to control a voltage of the second bit line during a programming operation of the memory cell, wherein the voltage controlling element comprises a Phase Change Memory cell.
9. The Phase Change Memory device of claim 8 wherein the Phase Change Memory cell is coupled between the second bit line and the voltage control word line.
10. A Phase Change Memory device comprising:
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element coupled to the second bit line to control a voltage of the second bit line during a programming operation of the memory cell;
a third bit line adjacent to the first bit line on an opposite side of the second bit line; and
a second voltage controlling element coupled to the third bit line to control a voltage of the third bit line during the programming operation of the memory cell, wherein the second voltage controlling element is coupled to the voltage control word line.
11. The Phase Change Memory device of claim 10 further comprising:
a third voltage controlling element coupled to the first bit line to control a voltage of the first bit line during a programming operation of the second memory cell;
a fourth bit line adjacent to the third bit line;
a fourth voltage controlling element coupled to the fourth bit line to control a voltage of the fourth bit line during the programming operation of the second memory cell; and
a second voltage control word line, wherein the third and the fourth voltage controlling elements are coupled to the second voltage control word line.
12. A method to program a first memory cell of Phase Change Memory device comprising:
applying a word line programming voltage to a first word line and a bit line programming voltage to a first bit line to write data into the first memory cell; and
applying a voltage to a voltage controlling element directly coupled to a second bit line to control the voltage of the second bit line and prevent data stored in a second memory cell coupled to the first word line from being altered by the writing data into the first memory cell.
13. A method to program a first memory cell of Phase Change Memory device comprising:
applying a word line programming voltage to a first word line and a bit line programming voltage to a first bit line to write data into the first memory cell; and
applying a voltage to a voltage controlling element coupled to a second bit line to control the voltage of the second bit line and prevent data stored in a second memory cell coupled to the first word line from being altered by the writing data into the first memory cell, wherein the voltage controlling element comprises a voltage controlling diode coupled between the second bit line and a voltage control word line.
14. The method of claim 13 , further comprising:
removing the bit line programming voltage from the first bit line to complete the programming operation of the first memory cell; and
applying a voltage to the voltage control word line during the removing the bit line programming voltage to control the voltage of the second bit line.
15. A wireless communication device, comprising:
a transceiver to receive over-the-air signals;
a processor core coupled to the transceiver; and
a Phase Change Memory coupled to the processor core, the Phase Change Memory comprising,
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element directly coupled to the second bit line to control the voltage of the second bit line during a programming operation of the memory cell.
16. The wireless communication device of claim 15 wherein the voltage controlling element is coupled to a voltage control word line.
17. A wireless communication device, comprising:
a transceiver to receive over-the-air signals;
a processor core coupled to the transceiver; and
a Phase Change Memory coupled to the processor core, the Phase Change Memory comprising,
a memory cell coupled to a first word line and to a first bit line;
a second bit line adjacent to the first bit line; and
a voltage controlling element coupled to the second bit line to control the voltage of the second bit line during a programming operation of the memory cell, wherein the voltage controlling element comprises a Phase Change Memory cell coupled between the second bit line and the voltage control word line.
18. A Phase Change Memory (PCM) device comprising:
a first and second PCM cells;
a first bit line coupled to the first PCM cell;
a second bit line coupled to the second PCM cell;
a first voltage control line coupled to the first bit line;
a second voltage control line coupled to the second bit line;
a first voltage regulating element directly coupled between the first PCM cell and the first voltage control line, wherein the first voltage regulating element to control a voltage of the first bit line during a programming operation of the second memory cell; and
a second voltage regulating element coupled between the second PCM cell and the second voltage control line, wherein the second voltage regulating element to control a voltage of the second bit line during a programming operation of the first memory cell.
19. A Phase Change Memory (PCM) device comprising:
a first and second PCM cells;
a first bit line coupled to the first PCM cell;
a second bit line coupled to the second PCM cell;
a first voltage control line coupled to the first bit line;
a second voltage control line coupled to the second bit line;
a first voltage regulating element coupled between the first PCM cell and the first voltage control line, wherein the first voltage regulating element to control a voltage of the first bit line during a programming operation of the second memory cell; and
a second voltage regulating element coupled between the second PCM cell and the second voltage control line, wherein the second voltage regulating element to control a voltage of the second bit line during a programming operation of the first memory cell, wherein the first and second voltage regulating elements comprise a PCM cell at a crossing of a bit line mask with a heater mask, wherein the bit line mask has a first pattern associated with the first bit line extending more than a second pattern associated with the second bit line on a side of the PCM device to intersect a pattern of the heater mask.
20. A Phase Change Memory (PCM) device comprising:
a first and second PCM cells;
a first bit line coupled to the first PCM cell;
a second bit line coupled to the second PCM cell;
a first voltage control line coupled to the first bit line;
a second voltage control line coupled to the second bit line;
a first voltage regulating element coupled between the first PCM cell and the first voltage control line, wherein the first voltage regulating element to control a voltage of the first bit line during a programming operation of the second memory cell; and
a second voltage regulating element coupled between the second PCM cell and the second voltage control line, wherein the second voltage regulating element to control a voltage of the second bit line during a programming operation of the first memory cell, wherein the first voltage control line is insulated from the second bit line and the second voltage control line is insulated from the first bit line.
21. The PCM device of claim 20 further comprising:
a first selection transistor coupled to the first voltage control line;
a first heater coupled to the first bit line;
a second selection transistor coupled to the first voltage control line; and
a second heater coupled to the second bit line, wherein a plug is coupled between the first selection transistor and the first heater to couple the first voltage control line and the first bit line, and a dielectric layer is interposed between the second selection transistor and the second heater to decouple the first voltage control line from the second bit line.