Serial parallel interface for data word architecture
View Patent ↗Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
1. A method comprising:
serially receiving a byte of data associated with a plurality of address bits that represent a starting byte address of a serial peripheral interface (SPI) data buffer; and
determining whether to place said byte of data on a lower byte or an upper byte of a word-aligned data bus based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer.
2. The method of claim 1 , further comprising:
determining whether to write said lower and/or said upper byte of said word-aligned data bus to said SPI data buffer based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer.
3. The method of claim 2 , further comprising serially receiving a plurality of data bytes associated with said starting byte address, wherein said plurality of data bytes comprises odd data bytes and even data bytes.
4. The method of claim 3 , further comprising:
placing said odd data bytes on said lower bytes of said word-aligned data bus if said starting byte address comprises an even address of said SPI data buffer.
5. The method of claim 3 , further comprising:
placing said even data bytes on said upper bytes of said word-aligned data bus if said starting byte address comprises an even address of said SPI data buffer.
6. The method of claim 3 , further comprising:
placing said odd data bytes on said upper bytes of said word-aligned data bus if said starting byte address comprises an odd address of said SPI data buffer.
7. The method of claim 3 , further comprising:
placing said even data bytes on said lower bytes of said word-aligned data bus if said starting byte address comprises an odd address of said SPI data buffer.
8. The method of claim 1 , further comprising:
writing data stored in said SPI data buffer into a nonvolatile memory if an end of said serially-received data is reached.
9. A apparatus comprising:
a controller to:
serially receive a byte of data associated with a plurality of address bits that represent a starting byte address of a serial peripheral interface (SPI) data buffer; and
determine whether to place said byte of data on a lower byte or an upper byte of a word-aligned data bus based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer.
10. The apparatus of claim 9 , said controller to determine whether to write said lower and/or said upper byte of said location of said word-aligned data bus to said SPI data buffer based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer.
11. The apparatus of claim 9 , said controller to serially receive a plurality of data bytes associated with said starting byte address, wherein said plurality of data bytes comprises odd data bytes and even data bytes.
12. The apparatus of claim 11 , said controller to place said odd data bytes on said lower bytes of said word-aligned data bus if said starting byte address comprises an even address of said SPI data buffer.
13. The apparatus of claim 11 , said controller to place said even data bytes on said upper bytes of said word-aligned data bus if said starting byte address comprises an even address of said SPI data buffer.
14. The apparatus of claim 11 , said controller to place said odd data bytes on said upper bytes of said word-aligned data bus if said starting byte address comprises an odd address of said SPI data buffer.
15. The apparatus of claim 11 , said controller to place said even data bytes on said lower bytes of said word-aligned data bus if said starting byte address comprises an odd address of said SPI data buffer.
16. The apparatus of claim 9 , said controller to write data stored in said SPI data buffer into a nonvolatile memory if an end of said serially-received data is reached.
17. A system comprising:
a memory device comprising an array of memory cells, said memory device further comprising a memory controller to:
in response to a write command, serially receive a byte of data to write to said array of memory cells, said byte of data associated with a plurality of address bits that represent a starting byte address of a serial peripheral interface (SPI) data buffer; and
determine whether to place said byte of data on a lower byte or an upper byte of a word-aligned data bus based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer; and
a processor to host one or more applications and to initiate said write command to said memory controller to provide access to said memory cells.
18. The system of claim 17 , said controller to determine whether to write said lower and/or said upper byte of said location of said word-aligned data bus to said SPI data buffer based, at least in part, on whether said starting byte address comprises an even address or an odd address of said SPI data buffer.
19. The system of claim 17 , said controller to serially receive a plurality of data bytes associated with said starting byte address, wherein said plurality of data bytes comprises odd data bytes and even data bytes.
20. The system of claim 17 , said controller to write data stored in said SPI data buffer into a nonvolatile memory if an end of said serially-received data is reached.