Method and apparatus to perform concurrent read and write memory operations
View Patent ↗Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array.
1. A method comprising:
reading particular contents of a first portion of a particular one of individual memory partitions in a memory array of a memory while writing to a second portion of said particular one of said individual memory partitions, wherein said reading comprises determining said particular contents of said first portion based, at least in part, on an error correction code (ECC) based, at least in part, on contents of said individual memory partitions;
suspending a calculation of said ECC in response to receiving a read request to read at least a part of said contents of said individual memory partitions; and
resuming said calculating said ECC subsequent to reading said at least a part of said contents of said individual memory partitions.
2. The method of claim 1 , wherein said determining said particular contents of said first portion is further based, at least in part, on contents of portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions.
3. The method of claim 2 , wherein said contents of said first portion of said particular one of said individual memory partitions are not used in said determining said particular contents of said first portion.
4. The method of claim 2 , further comprising:
reading in parallel, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
5. The method of claim 2 , further comprising:
reading in series, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
6. The method of claim 1 , wherein said writing to said second portion of said particular one of said individual memory partitions is in response to an internal operation initiated by said memory.
7. The method of claim 1 , wherein said first portion and said second portion of said particular one of said individual memory partitions share at least one group of sense amplifiers.
8. A memory microcontroller comprising:
at least one interface to connect to a memory array; and
electronic circuitry to:
read particular contents of a first portion of a particular one of individual memory partitions of said memory array while writing to a second portion of said particular one of said individual memory partitions, wherein said reading comprises determining said particular contents of said first portion based, at least in part, on an error correction code (ECC) based, at least in part, on contents of said individual memory partitions;
suspend a calculation of said ECC in response to receiving a read request to read at least a part of said contents of said individual memory partitions; and
resume said calculating said ECC subsequent to reading said at least a part of said contents of said individual memory partitions.
9. The memory microcontroller of claim 8 , wherein said determining said particular contents of said first portion is further based, at least in part, on contents of portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions.
10. The memory microcontroller of claim 9 , wherein said contents of said first portion of said particular one of said individual memory partitions are not used in said determining said particular contents of said first portion.
11. The memory microcontroller of claim 9 , further comprising a circuit to:
read in parallel, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
12. The memory microcontroller of claim 9 , further comprising a circuit to:
read in series, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
13. The memory microcontroller of claim 8 , wherein said first portion and said second portion of said particular one of said individual memory partitions share at least one sense amplifier.
14. A system comprising:
a memory device comprising a memory, said memory device further comprising a memory microcontroller to:
read particular contents of a first portion of a particular one of individual memory partitions in a memory array of a memory while writing to a second portion of said particular one of said individual memory partitions, wherein said reading comprises determining said particular contents of said first portion based, at least in part, on an error correction code (ECC) based, at least in part, on contents of said individual memory partitions;
suspend a calculation of said ECC in response to receiving a read request to read at least a part of said contents of said individual memory partitions; and
resume said calculating said ECC subsequent to reading said at least a part of said contents of said individual memory partitions; and
a processor to host one or more applications and to initiate a read command to said memory microcontroller to provide access to said memory array.
15. The system of claim 14 , wherein said determining said particular contents of said first portion is further based, at least in part, on contents of portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions.
16. The system of claim 15 , wherein said contents of said first portion of said particular one of said individual memory partitions are not used in said determining said particular contents of said first portion.
17. The system of claim 15 , further comprising a circuit to:
read in parallel, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
18. The system of claim 15 , further comprising a circuit to:
read in series, via a bus, said contents of said portions of said individual memory partitions that correspond to said first portion of said particular one of said individual memory partitions while performing said determining said particular contents of said first portion.
19. The system of claim 14 , wherein said first portion and said second portion of said particular one of said individual memory partitions share at least one sense amplifier.