IP Library Granted Patent US 8,626,990
Granted Patent B2
US 8,626,990 · App. 13/143,075 · Granted Jan 7, 2014

Non-volatile configuration for serial non-volatile memory

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Quick Facts
Patent No.
US 8,626,990
App. No.
13/143,075
Granted
Jan 7, 2014
Kind
B2
Abstract

Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.

Claims (26)

1. A method of configuring a memory, the method comprising:

reading a configuration value in a non-volatile configuration register in a serial non-volatile memory device at least in part in response to power being applied to the serial non-volatile memory device, the configuration value to specify one or more attributes of a read operation, wherein at least one of the one or more attributes comprises an execute-in-place mode for the read operation; and

modifying a performance of the read operation by the serial nonvolatile memory device based at least in part on the one or more attributes specified by the configuration value.

2. The method of claim 1 , wherein the serial non-volatile memory device comprises a serial flash memory device.

3. The method of claim 2 , wherein the one or more attributes of the read operation comprise a number of dummy cycles for the read operation.

4. The method of claim 2 , wherein the one or more attributes further comprise an output driver strength for the serial flash memory device.

5. The method of claim 1 , wherein the one or more attributes further comprise a minimum time before first access after power-up for the serial flash memory device.

6. The method of claim 1 , wherein the non-volatile configuration register comprises a plurality of flash memory cells.

7. The method of claim 1 , further comprising updating contents of the non-volatile configuration register at least in part in response to receiving a subsequent configuration value from a processor.

8. A serial non-volatile memory device, comprising:

a non-volatile configuration register to store a configuration value, the configuration value to specify one or more attributes of a read operation, wherein at least one of the one or more attributes comprises an execute-in-place mode for the read operation; and

a control unit configured to read the configuration value from the non-volatile configuration register at least in part in response to power being applied to the serial non-volatile memory device, the control unit configured to modify a performance of the read operation by the serial non-volatile memory device based at least in part on the one or more attributes specified by the configuration value.

9. The memory device of claim 8 , wherein the serial non-volatile memory device comprises a serial flash memory device.

10. The memory device of claim 9 , wherein the one or more attributes of the read operation comprise a number of dummy cycles for the read operation.

11. The memory device of claim 9 , wherein the one or more attributes further comprise an output driver strength for the serial flash memory device.

12. The memory device of claim 9 , wherein the one or more attributes further comprise a minimum time before first access after power-up for the serial flash memory device.

13. The memory device of claim 8 , wherein the non-volatile configuration register comprises a plurality of flash memory cells.

14. The memory device of claim 8 , wherein the non-volatile configuration register is configured to be updated at least in part in response to the serial non-volatile memory device receiving a subsequent configuration value from a processor.

15. A system, comprising:

a processor; and

a serial non-volatile memory device coupled to the processor, the memory device comprising:

a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a read operation, wherein at least one of the one or more attributes comprises an execute-in-place mode for the read operation; and

a control unit configured to read the configuration value from the non-volatile configuration register at least in part in response to power being applied to the serial non-volatile memory device, the control unit configured to modify a performance of the read operation by the serial non-volatile memory device based at least in part on the one or more attributes specified by the configuration value.

16. The system of claim 15 , wherein the one or more attributes of the read operation further comprise one or more of a number of dummy cycles for the read operation, an execute-in-place mode, an output driver strength, and/or a minimum time before first access after power-up for the serial non-volatile memory device.

17. The system of claim 15 , wherein the non-volatile configuration register comprises a plurality of flash memory cells and wherein the serial non-volatile memory device comprises a serial flash memory device.

18. The system of claim 17 , wherein the non-volatile configuration register is configured to be updated at least in part in response to the serial flash memory device receiving a subsequent configuration value from the processor.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: ROLANDI, PAOLO; LOSPALLUTI, SANDRA; BUFANO, RAFFAELE; ANDREOLI, STEFANO; ZERILLI, TOMMASO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026970/0343 →