Programming an array of resistance random access memory cells using unipolar pulses

1. A method of programming a non-volatile memory device, the method comprising:

providing information to said memory device;

subsequently initiating a transition from a set state to a reset state of a memory cell of said memory device to program said information in said memory cell in response to a write command, by applying a first portion of an electric pulse to drive said memory cell into a high-voltage unstable state; and

applying a second portion of said electric pulse during said transition to decrease a voltage of said electric pulse so as to return said memory cell to a stable state.

2. The method of claim 1 , wherein said non-volatile memory device comprises a resistance random access memory (RRAM).

3. The method of claim 2 , wherein said set state of said RRAM comprises a low-resistance state and said reset state of said RRAM comprises a high-resistance state.

4. The method of claim 1 , wherein said second portion of said electric pulse comprises a decaying resistor-capacitor (RC) voltage.

5. The method of claim 1 , wherein said memory cell comprises one of a plurality of resistance random access memory (RRAM) cells in an array.

6. The method of claim 2 , wherein a voltage across said memory cell in said stable state comprises a voltage less than a threshold switching voltage in a reset state of said memory cell.

7. The method of claim 2 , wherein a voltage across said memory cell in said high-voltage unstable state comprises a voltage greater than a threshold switching voltage in a reset state of said memory cell.

8. The method of claim 1 , wherein maintaining said memory cell in said high-voltage unstable state for longer than a particular time results in physical damage to or spurious programming of said memory cell.

9. A non-volatile memory device comprising:

a controller to:

receive information to be stored in said memory device;

subsequently initiate a transition from a set state to a reset state of a memory cell of said memory device, to program said information in said memory cell in response to a write command, by applying a first portion of an electric pulse to drive said memory cell into a high-voltage unstable state; and

apply a second portion of said electric pulse during said transition to decrease a voltage of said electric pulse so as to return said memory cell to a stable state.

10. The non-volatile memory device of claim 9 , wherein said non-volatile memory device comprises a resistance random access memory (RRAM).

11. The non-volatile memory device of claim 10 , wherein said set state of said RRAM comprises a low-resistance state and said reset state of said RRAM comprises a high-resistance state.

12. The non-volatile memory device of claim 9 , further comprising a resistor-capacitor (RC) circuit to generate said electric pulse.

13. The non-volatile memory device of claim 9 , wherein said memory cell comprises one of a plurality of resistance random access memory (RRAM) cells in an array.

14. The non-volatile memory device of claim 10 , wherein a voltage across said memory cell in said high-voltage unstable state comprises a voltage greater than a threshold switching voltage in a reset state of said memory cell.

15. The non-volatile memory device of claim 9 , wherein maintaining said memory cell in said high-voltage unstable state for longer than a particular time results in physical damage to said memory cell.

16. A system comprising:

a memory device comprising an array of memory cells, said memory device further comprising a memory controller to:

receive information to be stored in said memory device;

subsequently initiate a transition from a set state to a reset state of a memory cell of said memory array, to program said information in said memory cell in response to a write command, by applying a first portion of an electric pulse to drive said memory cell into a high-voltage unstable state; and

apply a second portion of said electric pulse during said transition to decrease a voltage of said electric pulse so as to return said memory cell to a stable state; and

a processor to host one or more applications and to initiate programming said memory cell.

17. The system of claim 16 , wherein said non-volatile memory device comprises a resistance random access memory (RRAM).

18. The system of claim 17 , wherein said set state of said RRAM comprises a low-resistance state and said reset state of said RRAM comprises a high-resistance state.

19. The system of claim 16 , wherein said second portion of said electric pulse comprises a decaying resistor-capacitor (RC) voltage.

20. The system of claim 17 , wherein a voltage across said memory cell in said high-voltage unstable state comprises a voltage greater than a threshold switching voltage in a reset state of said memory cell.