Persistent memory for processor main memory
View Patent ↗Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
1. A memory device comprising:
a memory controller adapted to communicate with a main memory shared by multiple processors having cache, at least one of said multiple processors comprising a local memory including persistent memory shared by at least one other processor of said multiple processors, said main memory comprising persistent memory, said memory controller further adapted to retrieve information from said persistent main memory to initialize, upon boot-up, said cache included in said multiple processors.
2. The memory device of claim 1 , wherein said cache comprises a translation lookaside buffer (TLB).
3. The memory device of claim 2 , wherein said information comprises initial values for said TLB.
4. The memory device of claim 1 , wherein said multiple processors individually include embedded memory, wherein at least one of said multiple processors includes said main memory.
5. The memory device of claim 1 , wherein said main memory comprises a single main memory shared among said multiple processors.
6. The memory device of claim 1 , wherein said multiple processors comprise multiple processing systems.
7. The memory device of claim 1 , further comprising:
a memory hierarchy including one or more levels of cache memory shared among said multiple processors.
8. The memory device of claim 7 , wherein at least a portion of said one or more levels of cache memory comprise persistent memory.
9. The memory device of claim 1 , wherein said persistent memory comprises phase change memory (PCM).
10. The memory device of claim 1 , wherein said cache comprises on-board cache.
11. A method comprising:
retrieving information from a persistent memory in a main memory shared among multiple processors having on-board cache, at least one of said multiple processors comprising a local memory including persistent memory shared by at least one other processor of said multiple processors; and
loading said information to said on-board cache to initialize, upon boot-up, said on-board cache.
12. The method of claim 11 , wherein said on-board cache comprises a translation lookaside buffer (TLB).
13. The method of claim 12 , wherein said information comprises initial values for said TLB.
14. The method of claim 11 , wherein said multiple processors individually include embedded memory, wherein at least one of said multiple processors includes said main memory.
15. The method of claim 11 , wherein said main memory comprises a single main memory shared among said multiple processors.
16. The method of claim 11 , further comprising:
managing said main memory in a memory hierarchy including one or more levels of cache memory shared among said multiple processors.
17. The method of claim 11 , wherein said persistent memory comprises phase change memory (PCM).
18. A system comprising:
a plurality of processing entities to host one or more applications, individual ones of said processing entities including an on-board cache, said on-board cache comprising persistent memory shared by at least one of the other processing entities;
a main memory shared by said plurality of processing entities having at least one interface to connect to said plurality of processing entities, wherein at least a portion of said main memory comprises persistent memory; and a memory controller to retrieve information from said persistent main memory to initialize, upon boot-up, said on-board cache in the multiple processors.
19. The system of claim 18 , wherein said on-board cache comprises a translation lookaside buffer (TLB).
20. The system of claim 19 , wherein said information comprises initial values for said TLB.
21. The system of claim 18 , wherein a processing entity of said plurality of processing entities comprise a local memory including persistent memory, wherein said persistent local memory is shared by at least one other processing entity of said plurality of processing entities.