Method for low power accessing a phase change memory device
View Patent ↗A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.
1. A method for accessing a phase change memory device, comprising:
providing a plurality of phase change memory cells connected at crosspoints of a plurality of bitlines and a plurality of wordlines;
grouping a first sub-plurality of bitlines in a first group and a second sub-plurality of bitlines in a second group;
selecting at least a bitline in the first and second groups;
supplying currents to the selected bitlines;
biasing a selected wordline,
wherein selecting at least a bitline in the first and second groups comprises selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.
2. A method according to claim 1 wherein grouping a first sub-plurality and grouping a second sub-plurality comprise grouping n bitlines in each sub-plurality, selecting the first bitline in the first group comprises selecting bitline BL<i> in the first group and selecting the second bitline comprises selecting bitline BL< 2 n− 1−i> in the second group.
3. A method according to claim 1 further comprising deselecting the first and the second bitline, selecting a third bitline in the first group, different from the first bitline, and, while the third bitline is still selected, selecting a fourth bitline in the second group which is arranged symmetrically to the third bitline in the first group.
4. A method according to claim 1 wherein grouping a first sub-plurality and grouping a second sub-plurality comprise grouping n bitlines in each sub-plurality, the method further comprising repeating the step of selecting symmetrical bitlines in the first and second sub-pluralities until reaching an n-th bitline in the first group.
5. A method according to claim 1 further comprising grouping a third sub-plurality of bitlines in a third group adjacent to the first and the second group, wherein when the first and second bitlines are still selected, selecting a bitline in the third group, the bitline in the third group being arranged symmetrically to a bitline in the first or the second group.
6. A method according to claim 1 further comprising writing phase change memory cells connected to the selected bitlines.
7. A method according to claim 1 further comprising reading phase change memory cells connected to the selected bitlines.
8. A method according to claim 1 further comprising:
providing a plurality of tiles aligned along a direction and coupled to a periphery circuitry, each tile including at least one wordline,
addressing a first tile and, while the first tile is still selected, selecting a second tiles arranged symmetrically to said first tile along said direction.
9. A phase change memory device comprising:
a plurality of bitlines (BL) including a first group of bitlines and a second group of bitlines;
a plurality of wordlines (WL), crossing the bitlines;
a plurality of phase change memory cells connected at crosspoints of the bitlines and the wordlines;
a selecting stage for selecting at least a bitline in the first and in the second groups;
a current generator to supply access current to the selected bitlines;
a biasing stage for biasing a selected wordline,
wherein said selecting stage comprises means for selecting a first bitline in the first group and, while the first bitline is still selected, selecting in the second group a second bitline which is arranged symmetrically to the first bitline in the first group.
10. A phase change memory according to claim 9 wherein the first and the second groups comprise each n bitlines, wherein the selecting stage comprises means for sequentially selecting a bitline BL<i> in the first group and a bitline BL< 2 n− 1−i> in the second group.
11. A phase change memory according to claim 9 wherein the current generator comprises a write stage.
12. A phase change memory according to claim 9 wherein the current generator comprise a sensing stage.
13. A phase change memory according to any of claim 9 wherein said wordlines are grouped in a plurality of tiles aligned along a direction and coupled to a periphery circuitry, the memory comprising means for addressing a first tile and for addressing a second tiles which is arranged symmetrically along said direction while the first tile is still addressed.