Memory buffer having accessible information after a program-fail
View Patent ↗A memory device, and a method of operating same, utilize a first memory buffer associated with a first memory array and a second memory buffer associated with a second memory array to maintain information subsequent to a program-fail event associated with the first memory array and to provide the information to the second memory array.
1. A method comprising:
initiating a program operation to write particular information to a first memory array via a first memory buffer;
maintaining said particular information in said first memory buffer subsequent to a program-fail event; and
subsequent to said program-fail event, writing said particular information to a second memory buffer associated with a second memory array.
2. The method of claim 1 , further comprising:
determining said program-fail event during said program operation;
retrieving said particular information from said first memory buffer; and
writing said particular information to the second memory array via the second memory buffer.
3. The method of claim 1 , wherein said first memory buffer comprises a NAND page buffer.
4. The method of claim 1 , wherein a memory device comprises a first memory partition and a second memory partition, said first memory partition comprising said first memory array and said first memory buffer, and said second memory partition comprising said second memory array and said second memory buffer, wherein said memory device comprises a NAND-based memory card to receive said particular information from a memory card controller.
5. The method of claim 1 , further comprising, subsequent to said program-fail event, instructing said first memory buffer to write said particular information from said first memory buffer to said first memory array.
6. The method of claim 1 , further comprising, subsequent to said program-fail event, reading said particular information stored in said first memory buffer.
7. A memory device comprising:
a memory controller to initiate a program operation to write particular information to a memory array;
a first memory buffer associated with a first portion of said memory array; and
a second memory buffer associated with a second portion of said memory array, wherein said first memory buffer is configured to receive said particular information from said memory controller, to store said particular information during said program operation, and to store said particular information subsequent to a program-fail event associated with the first portion of said memory array, wherein the first portion of said memory array receives said particular information from said memory controller via said first memory buffer and, subsequent to said program-fail event, the particular information is written to the second memory bufer and the second portion of said memory array receives said particular information via said second memory buffer.
8. The memory device of claim 7 , wherein said first memory buffer comprises a NAND page buffer.
9. The memory device of claim 7 , wherein said first memory buffer and the first portion of said memory array are disposed on a same die.
10. The memory device of claim 7 , wherein said memory device comprises a NAND-based memory card to receive said particular information from a memory card controller.
11. The memory device of claim 7 , wherein said memory controller, in response to said program-fail event, is further configured to instruct said first memory buffer to write said particular information from said first memory buffer to the first portion of said memory array.
12. The memory device of claim 7 , wherein said memory controller, in response to said program-fail event, is further capable of reading said particular information stored in said first memory buffer.
13. The memory device of claim 12 , wherein said memory controller, subsequent to said reading, is further capable of providing said particular information to said second memory buffer associated with the second portion of said memory array.
14. A system comprising:
a memory device comprising:
a memory controller to initiate a program operation to write particular information to a memory array;
a first memory buffer associated with a first portion of said memory array;
a second memory buffer associated with a second portion of said memory array, wherein said first memory buffer is configured to receive said particular information from said memory controller, to store said particular information during said program operation, and to store said particular information subsequent to a program-fail event associated with the first portion of said memory array, wherein the first portion of said memory array receives said particular information from said memory controller via said first memory buffer and subsequent to said program-fail event, the particular information is written to the second memory buffer and the second portion of said memory array receives said particular information via said second memory buffer; and
a processor to host one or more applications and to initiate write commands to said memory controller to provide access to said memory array.
15. The system of claim 14 , wherein said first memory buffer comprises a NAND page buffer internal to a NAND memory comprising said memory array.
16. The system of claim 14 , wherein said first memory buffer comprises a volatile memory.
17. The system of claim 14 , wherein said memory device comprises a NAND-based memory card.
18. The system of claim 14 , wherein said first memory buffer and the first portion of said memory array are disposed on a same die.
19. The system of claim 14 , wherein said memory device comprises a NAND-based memory card to receive said particular information from a memory card controller.