IP Library Granted Patent US 8,510,628
Granted Patent B2
US 8,510,628 · App. 12/617,661 · Granted Aug 13, 2013

Method and apparatuses for customizable error correction of memory

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Quick Facts
Patent No.
US 8,510,628
App. No.
12/617,661
Granted
Aug 13, 2013
Kind
B2
Abstract

Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data.

Claims (50)

1. An apparatus, comprising:

a memory array to store data;

an analog to digital sense unit coupled to the memory array, the analog to digital sense unit to sense analog signals associated with the memory array and to convert the analog signals into distributions of digital values;

an error-correcting code (ECC) unit coupled to the analog to digital sense unit, the ECC unit to receive the distributions of digital values from the analog to digital sense unit and to obtain error probability data having error probability values associated with the distributions of digital values; and

a configurable non-volatile look-up table coupled to the ECC unit, the configurable non-volatile look-up table to generate ECC parameters including the error probability data and provide the ECC parameters to the ECC unit for error correction, wherein the configurable non-volatile look-up table updates error probability data based on the distributions of digital values with error probability values being based on a distance of a digital value in the distribution from a reference level.

2. The apparatus of claim 1 , wherein the ECC unit to execute an ECC algorithm to provide error correction using the error probability data.

3. The apparatus of claim 1 , wherein the analog to digital sense unit to sense analog signals associated with memory cells of the memory array upon initiation of the apparatus.

4. The apparatus of claim 1 , wherein the analog to digital sense unit to sense analog signals associated with memory cells of the memory array upon given reading state of the memory array.

5. The apparatus of claim 1 , further comprising:

one or more additional memory arrays, wherein the ECC unit to provide error correction for two or more memory arrays.

6. A data processing device, comprising:

a processing unit having at least one processor core; and

system memory coupled to the processing unit, the system memory having an integrated circuit device comprising

a memory array to store data;

an analog to digital sense unit coupled to the memory array, the analog to digital sense unit to sense analog signals associated with the memory array and to convert the analog signals into distributions of digital values;

an error-correcting code (ECC) unit coupled to the analog to digital sense unit, the ECC unit to receive the distributions of digital values from the analog to digital sense unit and to obtain error probability data having error probability values associated with the distributions of digital values; and

a configurable non-volatile look-up table coupled to the ECC unit, the configurable non-volatile look-up table to generate ECC parameters including the error probability data and provide the ECC parameters to the ECC unit for error correction, wherein the configurable non-volatile look-up table updates error probability data based on the distributions of digital values with error probability values being based on a distance of a digital value in the distribution from a reference level.

7. The data processing device of claim 6 , wherein the ECC unit to execute an ECC algorithm to provide error correction using the error probability data.

8. The data processing device of claim 6 , wherein the digital values represent a current or voltage distribution of memory cells in the memory array.

9. A data processing device, comprising:

a processing unit having at least one processor core; and

system memory coupled to the processing unit, the system memory having an integrated circuit device comprising

a memory array to store data;

an analog to digital sense unit coupled to the memory array, the analog to digital sense unit to sense analog signals associated with the memory array and to convert the analog signals into distributions of digital values;

an error-correcting code (ECC) unit coupled to the analog to digital sense unit, the ECC unit to receive the distributions of digital values from the analog to digital sense unit and to obtain error probability data having error probability values associated with the distributions of digital values; and

a configurable non-volatile look-up table coupled to the ECC unit, the configurable non-volatile look-up table to generate ECC parameters including the error probability data and provide the ECC parameters to the ECC unit for error correction, wherein the non-volatile look-up table is configured to receive updated digital values based on variations in the cells current or variations in the resistance or threshold voltage distribution in the array.

10. The data processing device of claim 9 , wherein the non-volatile look-up table is external or embedded within the ECC unit.

11. A method, comprising:

storing data in a memory array;

sensing analog signals associated with the memory array using an analog to digital sense unit;

converting the analog signals into distributions of digital values using the analog to digital sense unit;

sending the distributions of digital values from the analog to digital sense unit to an error-correcting code (ECC) unit;

generating error probability data associated with each digital value;

providing ECC parameters including error probability data to the ECC unit using a non-volatile look-up table; and

updating the non-volatile look-up table with updated error information associated with the memory array upon initiation of a memory device or upon given reading state of the memory array.

12. The method of claim 11 , further comprising:

executing an ECC algorithm with the ECC unit to provide error correction using the error probability data.

13. A method, comprising:

storing data in a memory array;

sensing analog signals associated with the memory array using an analog to digital sense unit;

converting the analog signals into distributions of digital values using the analog to digital sense unit;

sending the distributions of digital values from the analog to digital sense unit to an error-correcting code (ECC) unit;

generating error probability data associated with each digital value; and

updating the non-volatile look-up table with updated error information associated with the memory array as a consequence of variations in the operating voltage or temperature detected by a suitable voltage sensor or a temperature sensor, respectively.

14. A method, comprising:

storing data in a memory array;

sensing analog signals associated with the memory array using an analog to digital sense unit;

converting the analog signals into distributions of digital values using the analog to digital sense unit;

sending the distributions of digital values from the analog to digital sense unit to an error-correcting code (ECC) unit; and

generating error probability data associated with each digital value, wherein the configurable non-volatile look-up table updates error probability data based on the distributions of digital values with error probability values being based on a distance of a digital value in the distribution from a reference level.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2010
From: BEDESCHI, FERDINANDO; AMATO, PAOLO; GASTALDI, ROBERTO
To: NUMONYX B.V.
Reel/Frame 024775/0264 →