Patent Application

App. No. 12/481,496

Abstract

Claims (45)

1 . A phase change memory cell comprising:

a pnp-BJT selection device;

a silicide contact region on an emitter of said pnp-BJT selection device;

an L-shaped vertical heater element extending along a wordline direction of said pnp-BJT selection device and in direct contact with said silicide contact region; and

a phase change material in direct contact with said L-shaped vertical heater element.

2 . The phase change memory cell of claim 1 , wherein said L-shaped vertical heater element is self-aligned with said phase change material extending along a bitline of said phase change memory cell.

3 . The phase change memory cell of claim 2 , wherein said emitter is an emitter pillar.

4 . The phase change memory cell of claim 3 , wherein said emitter pillar is part of a pnp-BJT array including plurality of emitter pillars shared by one base contact pillar.

5 . The phase change memory cell of claim 2 , wherein said L-shaped vertical heater element has a vertical wall and horizontal base with approximately the same thickness.

6 . The phase change memory cell of claim 2 , wherein said phase change material is a chalcogenide.

7 . The phase change memory cell of claim 3 , wherein said L-shaped vertical heater element includes a vertical wall directly above a center vertical axis of said emitter pillar.

8 . The phase change memory cell of claim 7 , wherein said L-shaped vertical heater element includes a horizontal base having a width of approximately half the width of said emitter pillar.

9 . The phase change memory cell of claim 3 , further comprising a spacer disposed on a horizontal base of said L-shaped vertical heater element, said spacer having a sidewall vertically aligned with a sidewall of said emitter pillar.

10 . The phase change memory cell of claim 9 , wherein said spacer has a width approximately half a width of said emitter pillar.

11 . The phase change memory cell of claim 4 , further comprising a second L-shaped vertical heater element, wherein said L-shaped vertical heater element is facing a first direction, and said second L-shaped vertical heater element is facing in a direction opposite the first direction.

12 . A phase change memory array comprising:

a plurality of selection devices;

a silicide contact region on each of said plurality of selection devices;

a plurality of L-shaped vertical heater elements extending along a wordline direction of said phase change memory array and in direct contact with said plurality of silicide contact regions; and

a phase change material in direct contact with said plurality of L-shaped vertical heater elements;

wherein said plurality of L-shaped vertical heater elements are self-aligned with said phase change material extending along a bitline direction of said phase change memory array.

13 . The phase change memory array of claim 12 , wherein said plurality of L-shaped vertical heater elements are separated by an array of trenches extending along a wordline direction of said phase change memory array.

14 . The phase change memory array of claim 13 , wherein said selection devices are pnp-BJT devices.

15 . A method of forming a phase change memory cell comprising:

depositing a first dielectric layer over a pnp-BJT selection device;

etching a trench in said first dielectric layer to expose a silicide contact region on an emitter of said pnp-BJT selection device;

depositing a conformal conductive layer on said first dielectric layer and in said trench and in direct contact with said silicide contact region;

depositing a second conformal dielectric layer on said conductive layer and in said trench, wherein said conductive layer and said second conformal dielectric layer do not entirely fill said trench;

anisotropically etching back said conductive layer and said second conformal dielectric layer on said first dielectric layer and in said trench; and

depositing a phase change material in direct contact with a top surface of said conductive layer.

16 . The method of claim 15 , further comprising:

depositing a third dielectric layer to completely fill said trench; and

planarizing to expose said first dielectric layer; and

depositing said phase change material in direct contact with said first dielectric layer, second conformal dielectric layer, third dielectric layer, and conductive layer.

17 . The method of claim 16 , further comprising etching back said phase change material and conductive layer to form an L-shaped heater element self-aligned with said phase change material in a bitline direction of said phase change memory cell.

18 . The method of claim 15 further comprising:

etching a plurality of trenches in said first dielectric layer to expose a plurality of silicide contact regions on a plurality of emitters;

depositing said conformal conductive layer in said trenches;

depositing said second conformal dielectric layer on said conductive layer and in said trenches, wherein said conductive layer and said second conformal dielectric layer do not entirely fill said trenches; and

anisotropically etching back said conductive layer and said second conformal dielectric layer on said first dielectric layer and in said trenches.

19 . The method of claim 18 , further comprising:

depositing a third dielectric layer to completely fill said plurality of trenches; and

planarizing to expose said first dielectric layer; and

depositing a phase change material in direct contact with said first dielectric layer, second conformal dielectric layer, third dielectric layer, and conductive layer.

20 . The method of claim 19 , further comprising etching back said phase change material and said conductive layer in a plurality of lines running parallel to a wordline direction of said phase change memory cell to form an array phase change memory cells including L-shaped heater elements self-aligned with said phase change material in a bitline direction of said array phase change memory cells.

Assignments (10)