Apparatus including a follower output buffer having an output impedance that adapts to a transmission line impedance
View Patent ↗Embodiments include but are not limited to apparatuses and systems including an output buffer including an input terminal for receiving an input signal, an output terminal for outputting an output signal, and a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage. Other embodiments may be described and claimed.
1. An apparatus comprising:
an active device having an output terminal;
a first follower circuit having an input terminal coupled to the output terminal of the active device for receiving an input signal from the active device,
the first follower circuit including:
a first NMOS transistor and a first PMOS transistor, a drain terminal of the first NMOS transistor coupled to a local supply voltage, and a drain terminal of the first PMOS transistor coupled to a local ground voltage; and
a second NMOS transistor and a second PMOS transistor, wherein the first and second NMOS transistors and the first and second PMOS transistors are arranged in a current mirror configuration, a gate terminal of the second NMOS transistor is coupled to a gate terminal of the first NMOS transistor, and a gate terminal of the second PMOS transistor is coupled to a gate terminal of the first PMOS transistor; and
a second follower circuit having an input terminal coupled to the output terminal of the first follower circuit, the second follower circuit including:
a third NMOS transistor and a third PMOS transistor, a drain terminal of the third NMOS transistor coupled to the local supply voltage, and a drain terminal of the third PMOS transistor coupled to the local ground voltage; and
a fourth NMOS transistor and a fourth PMOS transistor, wherein the third and fourth NMOS transistors and the third and fourth PMOS transistors are arranged in a current mirror configuration, a gate terminal of the fourth NMOS transistor is coupled to a gate terminal of the third NMOS transistor, and a gate terminal of the fourth PMOS transistor is coupled to a gate terminal of the third PMOS transistor.
2. The apparatus of claim 1 , wherein a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor are directly coupled to the input terminal of the second follower circuit.
3. The apparatus of claim 2 , wherein the input terminal of the first follower circuit is directly coupled to the source terminal of the second NMOS transistor and to the source terminal of the second PMOS transistor, and wherein the input terminal of the second follower circuit is directly coupled to the source terminal of the fourth NMOS transistor and to the source terminal of the fourth PMOS transistor.
4. The apparatus of claim 1 , wherein the apparatus is an output buffer stage.
5. The apparatus of claim 1 , further comprising a resistive device coupled to the output terminal of the second follower circuit.
6. The apparatus of claim 1 , wherein the output terminal is coupled to a transmission line, and wherein the follower circuit has an output impedance substantially adaptively matching an impedance of the transmission line.
7. The apparatus of claim 1 , further comprising a first control circuit, wherein the first control circuit includes an input terminal directly coupled to the output terminal of the active device, and further includes an output terminal directly coupled to the input terminal of the first follower circuit.
8. The apparatus of claim 7 , further comprising a second control circuit, wherein the second control circuit includes an input terminal directly coupled to the output terminal of the first follower circuit, and further includes an output terminal directly coupled to the input terminal of the second follower circuit.
9. A system comprising:
an output buffer stage including:
a first follower circuit including a first NMOS transistor and a first PMOS transistor, a drain terminal of the first NMOS transistor coupled to a local supply voltage, and a drain terminal of the first PMOS transistor coupled to a local ground voltage, and further including a second NMOS transistor and a second PMOS, wherein the first and second NMOS transistors and the first and second PMOS transistors are arranged in a current mirror configuration, a gate terminal of the second NMOS transistor is coupled to a gate terminal of the first NMOS transistor, and a gate terminal of the second PMOS transistor is coupled to a gate terminal of the first PMOS transistor;
a second follower circuit having an input terminal coupled to the output terminal of the first follower circuit, the second follower circuit including a third NMOS transistor and a third PMOS transistor, a drain terminal of the third NMOS transistor coupled to the local supply voltage, and a drain terminal of the third PMOS transistor coupled to the local ground voltage, and further including a fourth NMOS transistor and a fourth PMOS transistor, wherein the third and fourth NMOS transistors and the third and fourth PMOS transistors are arranged in a current mirror configuration, a gate terminal of the fourth NMOS transistor is coupled to a gate terminal of the third NMOS transistor, and a gate terminal of the fourth PMOS transistor is coupled to a gate terminal of the third PMOS transistor;
a memory device including an output terminal coupled to an input terminal of the output buffer stage;
a host logic device bus; and
a bus interface unit coupling the output buffer stage and the host logic device bus.
10. The system of claim 9 , wherein the memory device comprises memory cells selected from the group consisting of NOR flash memory cells, NAND flash memory cells, and phase change memory cells.
11. The system of claim 9 , wherein the output buffer stage includes an output terminal coupled to a transmission line, and wherein the first and second follower circuits have an output impedance substantially adaptively matching an impedance of the transmission line.
12. The system of claim 9 , wherein a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor are directly coupled to the input terminal of the second follower circuit.
13. The system of claim 12 , wherein the output terminal of the memory device is directly coupled to the source terminal of the second NMOS transistor and to the source terminal of the second PMOS transistor.
14. The system of claim 9 , wherein the output buffer stage, the memory device, and the bus interface unit form an embedded memory module.
15. The system of claim 14 , wherein the host logic device is a microcontroller or a digital signal processor, and the system is a selected one of a desktop or laptop computer, a server, a set-top box, a digital recorder, a game console, a personal digital assistant, a mobile phone, a digital media player, or a digital camera.
16. A method comprising:
providing a first follower circuit including a first NMOS transistor and a first PMOS transistor, a drain terminal of the first NMOS transistor coupled to a local supply voltage, and a drain terminal of the first PMOS transistor coupled to a local ground voltage, and further including a second NMOS transistor and a second PMOS, wherein the first and second NMOS transistors and the first and second PMOS transistors are arranged in a current mirror configuration, a gate terminal of the second NMOS transistor is coupled to a gate terminal of the first NMOS transistor, and a gate terminal of the second PMOS transistor is coupled to a gate terminal of the first PMOS transistor;
providing a second follower circuit having an input terminal coupled to the output terminal of the first follower circuit, the second follower circuit including a third NMOS transistor and a third PMOS transistor, a drain terminal of the third NMOS transistor coupled to the local supply voltage, and a drain terminal of the third PMOS transistor coupled to the local ground voltage, and further including a fourth NMOS transistor and a fourth PMOS transistor, wherein the third and fourth NMOS transistors and the third and fourth PMOS transistors are arranged in a current mirror configuration, a gate terminal of the fourth NMOS transistor is coupled to a gate terminal of the third NMOS transistor, and a gate terminal of the fourth PMOS transistor is coupled to a gate terminal of the third PMOS transistor;
receiving an input signal on an input terminal of the first follower circuit;
modifying, using the first follower circuit, an impedance of the input signal;
modifying, using the second follower circuit, an impedance of the modified input signal received from the first follower circuit; and
outputting an output signal from an output terminal of the second follower circuit onto a transmission line.
17. The method of claim 16 , further comprising providing a supply voltage on a drain terminal of the first NMOS transistor, and providing a local ground voltage to a drain terminal of the first PMOS transistor.
18. The method of claim 16 , further comprising driving the input signal by an active device including an output terminal directly coupled to the input terminal of the first follower circuit.
19. The method of claim 18 , wherein the driving comprises driving the input signal by a memory device.