Non-volatile memory
View Patent ↗Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate assembly with a floating gate and a control gate assembly is described. The control gate assembly includes a non-metal conductive control gate and a metal control gate in one embodiment. Additional embodiments are described, including use of a sacrificial nitride layer and forming contact recesses to create source or drain contacts, as other examples.
1. A method of fabricating a non-volatile memory device, comprising:
depositing a non-metal conductive control gate layer over a floating gate;
depositing a sacrificial nitride layer over the non-metal conductive control gate layer;
selectively etching the sacrificial nitride layer leaving a selectively etched control gate recess;
and further comprising:
forming more than one flash memory cell in the non-volaitle memory device comprising:
etching away portions of the non-metal conductive control gate layer and the sacrificial nitride layer to at least partially define boundary voids extending between separate vertical layered stacks;
depositing at least some inter cell material within the boundary voids;
etching one or more contact recesses in the inter cell material; and
depositing a metal within the one or more contact recesses to form a source contact or a drain contact for the more than one flash memory cells in the non-volatile memory device.
2. The method of claim 1 , wherein the depositing the non-metal conductive control gate layer over the floating gate further comprises:
depositing an interpoly dielectric layer over the floating gate; and
depositing the non-metal conductive control gate layer over the interpoly dielectric layer.
3. The method of claim 2 , wherein a tunnel layer was previously deposited and is formed below the floating gate.
4. The method of claim 1 , wherein the etching further comprises: planarizing surfaces of separate vertical stacks, following the depositing, to expose sacrificial nitride.
5. The method of claim 4 , wherein the planarizing further comprises:
removing excess inter cell material from the surfaces.
6. The method of claim 5 , wherein the removing comprises etching.
7. The method of claim 1 , and further comprising:
planarizing surfaces of separate vertical stacks following the deposition of a metal.
8. The method of claim 7 , wherein the planarizing further comprises:
removing excess metal from the surfaces.
9. The method of claim 8 , wherein the removing comprises etching.
10. The method of claim 1 , wherein the non-metal conductive control gate comprises a poly material.