Concurrent memory operations
View Patent ↗Subject matter disclosed herein relates to performing concurrent memory operations.
1. A method comprising:
unmapping virtual memory addresses corresponding to physical memory locations to where a first operation is to be performed;
performing said first operation, wherein unmapping said virtual memory addresses of said first operation is performed before performing said first operation; and
concurrently performing a second operation of a command received while performing said first operation if said second operation does not affect said unmapped virtual memory addresses, wherein said second operation is of a different type from said first operation, and wherein remapping said virtual memory addresses is performed before performing said second operation.
2. The method of claim 1 , further comprising:
issuing an exception in response to receiving said command if said second operation does affect said unmapped virtual memory addresses.
3. The method of claim 2 , further comprising:
delaying or denying execution of said command as a result of issuing said exception.
4. The method of claim 2 , further comprising:
suspending said first operation and performing said second operation as a result of issuing said exception.
5. The method of claim 4 , further comprising:
resuming said suspended first operation after performing said second operation.
6. The method of claim 5 , further comprising:
unmapping said virtual memory addresses before resuming said suspended first operation.
7. The method of claim 1 , wherein said first operation type comprises a read operation, a write operation, or an erase operation.
8. The method of claim 7 , wherein said second operation type comprises a read operation, a write operation, or an erase operation, exclusive of said first operation type.
9. A memory device comprising:
a memory controller to perform a first operation on a first portion of a memory array corresponding to a first set of physical addresses; and
a memory management unit (MMU) coprocessor to unmap virtual memory addresses associated with said first set of physical addresses wherein the MMU coprocessor is configured to unmap said virtual memory addresses before performing said first operation, wherein said memory controller is adapted to concurrently perform the second operation without suspending said first operation if said second operation does not access said first set of physical addresses, and wherein said second operation is of a different type from said first operation; wherein the MMU coprocessor is configured to remap said virtual memory addresses before performing said second operation.
10. The memory device of claim 9 , wherein said first operation type comprises a read operation, a write operation, or an erase operation.
11. The memory device of claim 10 , wherein said second operation type comprises a read operation, a write operation, or an erase operation, exclusive of said first operation type.
12. The memory device of claim 9 , wherein said MMU coprocessor is adapted to delay or deny accesses by said second operation of said first set of physical addresses during said first operation.
13. The memory device of claim 9 , wherein said MMU coprocessor is adapted to flag as invalid accesses affecting said first portion of said memory array by said second operation during said first operation.
14. The memory device of claim 9 , wherein said MMU coprocessor is adapted to remap virtual memory addresses to physical addresses corresponding to said first portion of said memory array to allow said second operation to be performed.
15. The memory device of claim 9 , wherein said memory array comprises NOR flash memory cells.
16. The memory device of claim 9 , wherein said memory device is incorporated in at least one of the following: a desktop computer, a laptop computer, a workstation, a server device, a personal digital assistant, a mobile communication device, or any combination thereof.
17. A system comprising:
a memory device including a first portion of a memory array corresponding to a first set of physical addresses;
a memory controller to perform a first operation on said first portion of said memory array;
a memory management unit (MMU) coprocessor to unmap virtual memory addresses associated with said first set of physical addresses, wherein the MMU coprocessor is configured to unmap said virtual memory addresses before performing said first operation, wherein said memory controller is adapted to concurrently perform a second operation without suspending said first operation if said second operation does not access said first set of physical addresses, and wherein said second operation is of a different type from said first operation, wherein the MMU coprocessor is configured to remap said virtual memory addresses before performing said second operation; and
a processor to host one or more applications and to initiate said first operation or said second operation to provide access to said first portion of said memory array.
18. The system of claim 17 , wherein said first operation type comprises a read operation, a write operation, or an erase operation.
19. The system of claim 18 , wherein said second operation type comprises a read operation, a write operation, or an erase operation, exclusive of said first operation type.
20. The system of claim 17 , wherein said MMU coprocessor is adapted to flag as invalid accesses affecting said first portion of memory by said second operation during said first operation.
21. The system of claim 17 , wherein said MMU coprocessor is adapted to delay or deny accesses by said second operation of said first set of physical addresses during said first operation.
22. The system of claim 17 , wherein said system is incorporated in at least one of the following: a desktop computer, a laptop computer, a workstation, a server device, a personal digital assistant, a mobile communication device, or any combination thereof.