Dynamic range unlock or lock memory device and method to operate the same
View Patent ↗A non-volatile memory device with dynamic allocable regions that are unlocked or locked. Unlocking and/or locking is performed on one region or on multiple regions simultaneously, each region being identified by respective start address and end address. The start and end addresses of a dynamic allocable region need not coincide with physical addresses of a partition.
1. A method comprising:
receiving at least one address of at least one memory cell of a memory device to be locked, wherein when a memory cell of the memory device is locked data stored by that cell cannot be modified by a user, wherein the receiving the at least one address comprises receiving a range of addresses of memory cells defining a region of memory cells to be locked, and wherein the receiving the range of addresses comprises receiving a start address to define a first boundary of the region;
receiving a lock command to lock the at least one memory cell of the memory device; and
executing the lock command to lock the at least one memory cell of the memory device.
2. The method of claim 1 , wherein the receiving the range of addresses further comprises:
receiving an end address to define a second boundary of the region.
3. The method of claim 1 , wherein the memory device comprises:
a plurality of partitions, wherein each partition has a plurality of addresses to store data; and
at least one register to receive the lock command and the at least one address of the at least one memory cell to be locked.
4. The method of claim 3 , wherein the at least one register further comprises:
a plurality of registers, wherein each partition of the plurality of partitions is associated with at least one register of the plurality of register.
5. The method of claim 1 , wherein the receiving the range of addresses of memory cells defining the region of memory cells to be locked comprises:
receiving a region identifier, wherein the memory device is partitioned into different regions of addresses; and
identifying a region to be locked based on the region identifier.
6. A method comprising:
receiving at least one address of at least one memory cell of a memory device to be locked, wherein when a memory cell of the memory device is locked data stored by that cell cannot be modified by a user;
receiving a lock command to lock the at least one memory cell of the memory device;
executing the lock command to lock the at least one memory cell of the memory device
defining a rule to be matched by the received at least one address; and
outputting an error message when the rule is not matched.
7. A memory device comprising:
a data region of independently addressable memory cells to store data, wherein the data region is partitioned into a plurality of regions;
an information region to receive information associated with at least one addressable memory cell of a region to be locked, wherein the information is indicative of a position and a range of the region to be locked, and wherein the information region comprises a first register to receive a start address of the region to be locked.
8. The memory device of claim 7 , wherein the information region further comprises a second register to receive an end address of the region to be locked.
9. The memory device of claim 7 , wherein the information region comprises:
a plurality of registers divided in sub-pluralities to receive the information, wherein each register of each sub-plurality is associated to a corresponding partition in the data region.
10. The memory device of claim 7 , wherein the information region comprises:
a plurality of registers and each register of the plurality of registers is associated to a particular region to be locked.
11. The memory device of claim 7 , wherein the information region is part of an overlay window.
12. The memory device of claim 11 , wherein the overlay window comprises memory vendor specific registers to receive the information.
13. The memory device of claim 11 , wherein the memory device conforms to a JEDEC 42.6 standard.
14. The memory device of claim 7 , further comprising:
a validity bit associated to a first register to assert/de-assert a validity of data contained in the first register.
15. The memory device of claim 7 , further comprising:
a write protection connection to enable data modification only if a pre-defined logic value is applied to the write protect connection.
16. The memory device of claim 7 , wherein the memory cells of the data region are one of phase change memory cells, ferroelectric memory cells, or magnetic memory cells.
17. A system comprising:
a processor;
a memory coupled to the processor, wherein the memory includes:
a data region of independently addressable memory cells to store data, wherein the data region is partitioned into a plurality of regions;
an information region to receive information associated with at least one addressable memory cell of a region to be locked, wherein the information is indicative of a position and a range of the region to be locked, and wherein the information region comprises a first register to receive a start address of the region to be locked.