Flash memory having multi-level architecture
View Patent ↗Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.
1. A method of fabricating a memory device, the method comprising:
forming peripheral circuitry on a substrate;
covering said peripheral circuitry and said substrate with an interlayer dielectric layer; and
forming a stack of one or more levels of memory arrays on said interlayer dielectric layer, wherein forming a first level of said one or more levels of memory arrays comprises:
at least partially covering said interlayer dielectric layer with a polysilicon thin film;
patterning a portion of said polysilicon thin film to form substantially parallel multiple polysilicon lines;
at least partially covering said polysilicon thin film and said multiple polysilicon lines with an oxide-nitride-oxide (ONO) stack; and
at least partially covering said ONO stack with a metal layer.
2. The method of claim 1 , further comprising:
exposing said polysilicon thin film by removing a portion of said metal layer and said ONO stack to define parallel gate lines.
3. The method of claim 1 , further comprising:
exposing said polysilicon thin film by removing a portion of said metal layer and said ONO stack; and
replacing said removed portion of said metal layer and said ONO stack with a conductive material to form a source contact.
4. The method of claim 1 , further comprising:
forming a first drain contact between two consecutive memory array levels;
aligning a polysilicon line of one of said two consecutive memory array levels on said first drain contact; and
forming a second drain contact between said polysilicon line and a third consecutive memory array level.
5. The method of claim 1 , further comprising:
after forming said one or more memory array levels, forming a drain contact among said memory array levels.
6. The method of claim 1 , wherein said memory arrays comprise charge trap NAND memory cell arrays.
7. A memory device comprising:
peripheral circuitry on a substrate;
an interlayer dielectric layer to cover said peripheral circuitry; and
one or more levels of memory arrays formed on said interlayer dielectric layer, wherein said peripheral circuitry is disposed between said substrate and said interlayer dielectric layer, the one or more levels of memory arrays comprising:
a polysilicon thin film to at least partially cover said interlayer dielectric layer;
an oxide-nitride-oxide (ONO) stack and a metal layer to at least partially cover said polysilicon thin film;
an opening in a portion of said ONO stack and said metal layer to expose a portion of said polysilicon thin film; and
a source contact disposed in said opening.
8. The memory device of claim 7 , wherein said one or more levels of memory arrays cover at least a portion of said peripheral circuitry.
9. The memory device of claim 7 , wherein said memory arrays comprise said ONO stack to trap charge carriers in individual memory cells.
10. The memory device of claim 7 , further comprising:
a first drain contact between two consecutive memory array levels; and
a second drain contact between a poly silicon bit line of one of said two consecutive memory array levels and a third consecutive memory array level.
11. The memory device of claim 7 , further comprising:
a drain contact extending across two or more said memory array levels.
12. The memory device of claim 7 , further comprising parallel gate lines on said one or more levels of memory arrays.
13. The memory device of claim 7 , wherein said memory arrays comprise charge trap NAND memory cell arrays.
14. A system comprising:
a memory device comprising:
peripheral circuitry on a substrate;
an interlayer dielectric layer to cover said peripheral circuitry; and
one or more levels of memory arrays on said interlayer dielectric layer, the one or more levels of memory array comprising:
a polysilicon thin film to at least partially cover said interlayer dielectric layer;
an oxide-nitride-oxide (ONO) stack and a metal layer to at least partially cover said ONO stack;
an opening in a portion of said ONO stack and said metal layer to expose a portion of said polysilicon thin film; and
a source contact disposed in said opening;
a memory controller to operate said memory device, and
a processor to host one or more applications and to initiate write commands to said memory controller to provide access to memory cells in said memory arrays.
15. The system of claim 14 , wherein said memory device further comprises:
a first drain contact between two consecutive memory array levels; and
a second drain contact between a poly silicon bit line of one of said two consecutive memory array levels and a third consecutive memory array level.
16. The system of claim 14 , wherein said memory device further comprises:
a drain contact extending across two or more said memory array levels.
17. The system of claim 14 , wherein said memory arrays comprise charge trap NAND memory cell arrays.